NCP161AFCT300T2G ON Semiconductor

XXX M DATA SHEET www.onsemi.com LDO Regulator for RF and WLCSP4 WLCSP4 Analog Circuits - Ultra-Low CASE 567JZ CASE 567KA Noise and High PSRR 1 450 mA 1 XDFN4 SOT235 CASE 711AJ CASE 527AH NCP161 MARKING DIAGRAMS The NCP161 is a linear regulator capable of supplying 450 mA output current. Designed to meet the requirements of RF and analog circuits, the NCP161 device provides low noise, high PSRR, low quiescent current, and very good load/line transients. The device is X X designed to work with a 1 F input and a 1 F output ceramic capacitor. A1 A1 It is available in two thickness ultrasmall 0.35P, 0.64 mm x 0.64 mm Chip Scale Package (CSP) and XDFN4 0.65P, 1 mm x 1 mm. Features Operating Input Voltage Range: 1.9 V to 5.5 V XX M Available in Fixed Voltage Option: 1.8 V to 5.14 V 1 2% Accuracy Over Load/Temperature X, XX, XXX = Specific Device Code Ultra Low Quiescent Current Typ. 18 A M = Date Code Standby Current: Typ. 0.1 A Very Low Dropout: 150 mV at 450 mA PIN CONNECTIONS (Top Views) Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz Ultra Low Noise: 10 V RMS Stable with a 1 F Small Case Size Ceramic Capacitors 5 IN OUT 1 Available in WLCSP4 0.64 mm x 0.64 mm x 0.4 mm GND 2 WLCSP4 0.64 mm x 0.64 mm x 0.33 mm XDFN4 1 mm x 1 mm x 0.4 mm 3 EN 4 NC SOT235 2.9 mm x 2.8 mm x 1.2 mm These Devices are PbFree and are RoHS Compliant IN OUT IN EN 43 Typical Applications A2 A1 Batterypowered Equipment EPAD Wireless LAN Devices B1 B2 Smartphones, Tablets 12 Cameras, DVRs, STB and Camcorders OUT GND EN GND ORDERING INFORMATION See detailed ordering and shipping information on page 17 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 18 NCP161/DNCP161 V V OUT IN IN OUT NCP161 C EN IN C OUT 1 F ON 1 F Ceramic Ceramic GND OFF Figure 1. Typical Application Schematics IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin No. Pin CSP4 SOT235 XDFN4 Name Description A1 1 4 IN Input voltage supply pin A2 5 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. B1 3 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN B2 2 2 GND Common ground connection EPAD EPAD Expose pad should be tied to ground plane for better power dissipation www.onsemi.com 2