NCP167 LDO Regulator - Ultra-Low Noise, High PSRR, RF and Analog Circuits 700 mA www.onsemi.com The NCP167 is a linear regulator capable of supplying 700 mA output current. Designed to meet the requirements of RF and analog circuits, the NCP167 device provides low noise, high PSRR, low MARKING quiescent current, and very good load/line transients. The device is DIAGRAMS designed to work with a 1 F input and a 1 F output ceramic capacitor. It is available in two thickness ultrasmall 0.35P, 0.65 mm x 0.65 mm X M Chip Scale Package (CSP) and XDFN4 0.65P, 1 mm x 1 mm. WLCSP4 A1 CASE 567JZ Features Operating Input Voltage Range: 1.9 V to 5.5 V Available in Fixed Voltage Option: 1.8 V to 5.2 V 1 XX M 2% Accuracy Over Load/Temperature XDFN4 1 Ultra Low Quiescent Current Typ. 12 A CASE 711AJ Standby Current: Typ. 0.1 A Very Low Dropout: 210 mV at 700 mA X or XX = Specific Device Code M = Date Code Ultra High PSRR: Typ. 85 dB at 20 mA, f = 1 kHz Ultra Low Noise: 8.5 V RMS Stable with a 1 F Small Case Size Ceramic Capacitors PIN CONNECTIONS Available in WLCSP4 0.65 mm x 0.65 mm x 0.33 mm IN OUT XDFN4 1 mm x 1 mm x 0.4 mm These Devices are PbFree, Halogen Free/BFR Free and are RoHS A2 A1 Compliant B1 B2 Typical Applications Batterypowered Equipment EN GND Wireless LAN Devices (Top View) Smartphones, Tablets Cameras, DVRs, STB and Camcorders V V OUT IN IN OUT NCP167 C EN IN C OUT 1 F 1 F ON Ceramic Ceramic GND (Top View) OFF ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. Figure 1. Typical Application Schematics Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: September, 2019 Rev. 3 NCP167/DNCP167 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin CSP4 XDFN4 Name Description A1 4 IN Input voltage supply pin A2 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. B1 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN B2 2 GND Common ground connection EPAD EPAD Expose pad should be tied to ground plane for better power dissipation ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Input Voltage (Note 1) V V 0.3 V to 6 IN Output Voltage V 0.3 to V + 0.3, max. 6 V V OUT IN Chip Enable Input V 0.3 to V + 0.3, max. 6 V V CE IN Output Short Circuit Duration t unlimited s SC Maximum Junction Temperature T 150 C J Storage Temperature T 55 to 150 C STG ESD Capability, Human Body Model (Note 2) ESD 2000 V HBM ESD Capability, Machine Model (Note 2) ESD 200 V MM Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Refer to ELECTRICAL CHARACTERISTICS and APPLICATION INFORMATION for Safe Operating Area. 2. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per EIA/JESD22A114 ESD Machine Model tested per EIA/JESD22 A115 Latchup Current Maximum Rating tested per JEDEC standard: JESD78. THERMAL CHARACTERISTICS Rating Symbol Value Unit Thermal Characteristics, WLCSP4 (Note 3) 108 Thermal Resistance, JunctiontoAir R C/W JA Thermal Characteristics, XDFN4 (Note 3) 198 Thermal Resistance, JunctiontoAir 3. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51 7 www.onsemi.com 2