NCP3136 Integrated Synchronous Buck Converter 6 A NCP3136 is a fully integrated synchronous buck converter for 3.3 V www.onsemi.com and 5 V step down applications. It can provide up to 6.5A instantaneous current. NCP3136 supports high efficiency, fast transient response and provides power good indicator. The control MARKING scheme includes two operation modes: FCCM and automatic DIAGRAM CCM/DCM. In automatic CCM/DCM mode, the controller can smoothly switch between CCM and DCM, where converter runs at 1 3136 reduced switching frequency with much higher efficiency. NCP3136 ALYW QFN16 is available in 3 mm x 3 mm QFN16 pin package. CASE 485DA Features 3136 = Specific Device Code A = Assembly Location High Efficiency in Both CCM and DCM L = Wafer Lot Operation Frequency: 1.1 MHz Y = Year Support MLCC Output Capacitor W = Work Week = PbFree Package Small Footprint, 3 mm x 3 mm, 16pin QFN Package (Note: Microdot may be in either location) 2.9 V to 5.5 V Wide Conversion Voltage Range Output Voltage Range from 0.6 V to 0.84 X V IN PINOUT DIAGRAM Automatic PowerSaving Mode Voltage Mode Control Support Prebias Startup Functionality 16 15 14 13 Output Discharge Operation EN VDD 1 12 OverTemperature Protection AGND Builtin OverVoltage, UnderVoltage and OverCurrent Protection NC 2 11 NCP3136 Power Good Indicator PGD FB 3 10 This Device is PbFree and is RoHS Compliant VBST COMP 4 9 Applications 5 V Step Down Rail 56 7 8 3.3 V Step Down Rail ORDERING INFORMATION Device Package Shipping NCP3136MNTXG QFN16 3000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: August, 2019 Rev. 3 NCP3136/D SW PGND PGND SW VIN SW VIN PSNCP3136 VIN BST UVLO NC OSC Ramp Control Logic DRVH & Mode PS PWM Logic Selection SS EN SWN COMP VREF + DRVL + E/A Power Good FB PGND UVP, OVP, UVLO, Overtemperature OCP PGD and Vout discharge VDD AGND Figure 1. Block Diagram PIN DESCRIPTION Pin No. Symbol Description 1 EN Logic control to enabling the switcher. Internally pulled up to VDD with a 1.35 M resistor. 2 NC Not connected. 3 PGD Open drain power good output. 4 BST Gate drive voltage for high side FET. Connect capacitor from this pin to SWN. 5,6,7 SWN Switch node between highside MOSFET and lowside MOSFET. 8 PS Mode configuration pin: Connecting to ground: Forced CCM Pulled high or floating (internal pulled high): Forced CCM Connect with 24.3 k to GND: Automatic CCM/DCM Connect with 57.6 k to GND: Automatic CCM/DCM Connect with 105 k to GND: Automatic CCM/DCM Connect with 174 k to GND: Automatic CCM/DCM 9 COMP Output of the error amplifier. 10 FB Feedback pin. Connect to resistor divider to set up the desired output voltage. 11 AGND Analog ground 12 VDD Power supply input for control circuitry. 13,14 VIN Power input for power conversion and gate driver supply. 15,16 PGND Power ground www.onsemi.com 2