NCP51145 DDR 1.8 Amp Source / Sink V Termination Regulator TT The NCP51145 is a linear regulator designed to supply a regulated V termination voltage for DDRII, DDRIII, LPDDRIII and TT DDRIV memory applications. The regulator is capable of actively www.onsemi.com sourcing and sinking 1.8 A peak currents while regulating an output voltage to within 20 mV. The output termination voltage is regulated to track V / 2 by two external voltage divider resistors connected DDQ MARKING to the PV , GND, and V pins. CC REF DIAGRAMS The NCP51145 incorporates a highspeed differential amplifier to 8 provide ultrafast response to line and load transients. Other features SOIC8 EP 51145 include source/sink current limiting, softstart and onchip thermal 8 D SUFFIX AYWW shutdown protection. 1 CASE 751BU Features 1 For DDR V Applications, Source/Sink Currents: TT 1 DFN8 Supports DDRII to 1.8 A, DDRIII to 1.5 A XXM MN SUFFIX CASE 506AA Supports LPDDRIII and DDRIV to 1.2 A 1 Stable Using CeramicOnly (Very Low ESR) Capacitors 51145 = Specific Device Code Integrated Power MOSFETs XX = Specific Device Code M = Date Code High Accuracy V Output at FullLoad TT A = Assembly Location Fast Transient Response Y = Year Builtin SoftStart WW = Work Week = PbFree Package Shutdown for Standby or Suspend Mode (Note: Microdot may be in either location) Integrated Thermal and CurrentLimit Protection V Remote Sense Available in the DFN8 2x2mm Package TT PIN CONNECTIONS These Devices are PbFree and are RoHS Compliant 18 18 Typical Applications PVCC V CC PVCC NC NC V DDRII / DRIII / DDRIV SDRAM Termination Voltage TT GND NC V NC TTS Motherboard, Notebook, and VGA Card Memory Termination VREF V CC GND VREF Set Top Box, Digital TV, Printers V NC TT SOIC8 EP DFN8 2x2, 0.5P Low Power DDR3LP (Top Views) ORDERING INFORMATION Device Package Shipping NCP51145PDR2G SOIC8 2500 / Tape & (PbFree) Reel NCP51145MNTAG DFN8 3000 / Tape & (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: April, 2017 Rev. 3 NCP51145/DNCP51145 NCP51145 SO8EP Package PV = 1.0 to 5.5 V* CC 1 R4 5 V 6 PV CC V CC 2.2 C2 C3 R2 2 100k GND 3 V = 0.6 to 2.5 V* TT V 4 REF V TT C1 R1 Enable C4 100k R3 EP C1 = 1 to 100 nF Ceramic C4 = 10 F Ceramic *For DDR2: PV = 1.8 V, V = 0.9 V CC TT C2 = 10 F Ceramic R3 = Optional V Discharge Resistor DDR3: PV = 1.5 V, V = 0.75 V TT CC TT C3 = 1 F NCh MOSFET = Optional Enable / Disable DDR4: PV = 1.2 V, V = 0.60 V CC TT Figure 1. Application Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. SO8EP DFN8 Pin Name Description 1 1 PV Input voltage which supplies current to the output pin. C C CC IN OUT 2 4 GND Common Ground 3 5 V Buffered reference voltage input equal to of V and active low shutdown pin. An REF DDQ external resistor divider dividing down the PV voltage creates the regulated output CC voltage. Pulling the pin to ground (0.15 V maximum) turns the device off. 4 2 V Regulator output voltage capable of sourcing and sinking current while regulating the TT output rail. C = 10 F Ceramic, or greater OUT 5, 7, 8 3, 7 NC True No Connect 6 8 V The V pin is a 5 V input pin that provides internal bias to the controller. PV should CC CC CC always be kept lower or equal to V . CC 6 V V Sense TTS TT EP EP EPAD Pad for thermal connection. The exposed pad must be connected to the ground plane using multiple vias for maximum power dissipation performance. www.onsemi.com 2