NCP81062MNTWG ON Semiconductor

NCP81062 VR12 Compatible Synchronous Buck MOSFET Drivers The NCP81062 is a high performance dual MOSFET gate driver optimized to drive the gates of both highside and lowside power NCP81062 BST DRVH 1 PWM SW FLAG 9 EN GND VCC DRVL (Top View) Figure 1. Pin Diagram BST VCC DRVH PWM Logic SW AntiCross Conduction VCC DRVL EN ZCD Detection UVLO PreOV Fault Figure 2. Block Diagram Table 1. Pin Descriptions Pin No. Symbol Description 1 BST Floating bootstrap supply pin for high side gate driver. Connect the bootstrap capacitor between this pin and the SW pin. 2 PWM Control input. The PWM signal has three distinctive states: Low = Low Side FET Enabled, Mid = Diode Emulation Enabled, High = High Side FET Enabled. 3 EN Logic input. A logic high to enable the part and a logic low to disable the part. 4 VCC Power supply input. Connect a bypass capacitor (0.1 F) from this pin to ground. 5 DRVL Low side gate drive output. Connect to the gate of low side MOSFET. 6 GND Bias and reference ground. All signals are referenced to this node (QFN Flag). 7 SW Switch node. Connect this pin to the source of the high side MOSFET and drain of the low side MOSFET. 8 DRVH High side gate drive output. Connect to the gate of high side MOSFET. 9 FLAG Thermal flag. There is no electrical connection to the IC. Connect to ground plane.