NCV8161 LDO Regulator - Ultra-Low Noise, High PSRR, RF and Analog Circuits 450 mA www.onsemi.com The NCV8161 is a linear regulator capable of supplying 450 mA output current. Designed to meet the requirements of RF and analog MARKING circuits, the NCV8161 device provides low noise, high PSRR, low DIAGRAM quiescent current, and very good load/line transients. The device is 5 designed to work with a 1 F input and a 1 F output ceramic capacitor. It is available in TSOP5 and XDFN4 packages. XXXAYW TSOP5 5 CASE 483 1 Features 1 Operating Input Voltage Range: 1.9 V to 5.5 V XXX = Specific Device Code Available in Fixed Voltage Option: 1.8 V to 5.14 V A = Assembly Location 2% Accuracy Over Temperature Y = Year W = Work Week Ultra Low Quiescent Current Typ. 18 A = PbFree Package Standby Current: Typ. 0.1 A (Note: Microdot may be in either location) Very Low Dropout: 225 mV at 450 mA Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz XDFN4 Ultra Low Noise: 10 V RMS XX M CASE 711AJ 1 Stable with a 1 F Small Case Size Ceramic Capacitors 1 Available in TSOP5 and XDFN4 Packages XX = Specific Device Code NCV Prefix for Automotive and Other Applications Requiring M = Date Code Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable Device Temperature Grade 1: 40C to +125C Ambient Operating Temperature Range PIN CONNECTIONS These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant IN OUT 15 Typical Applications GND 2 Parking Camera Modules NC/ADJ EN34 Wireless Handsets, Wireless LAN, Bluetooth , Zigbee (Top View) Automotive Infotainment Systems Other Battery Powered Applications IN EN V V OUT IN 4 3 IN OUT NCV8161 C EN IN C OUT EPAD 1 F ON 1 F Ceramic Ceramic GND OFF 1 2 OUT GND Figure 1. Typical Application Schematic (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 14 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: September, 2019 Rev. 1 NCV8161/DNCV8161 IN ENABLE THERMAL EN LOGIC SHUTDOWN BANDGAP MOSFET REFERENCE INTEGRATED DRIVER WITH SOFT START CURRENT LIMIT OUT * ACTIVE DISCHARGE Version A only EN GND Figure 2. Simplified Schematic Block Diagram PIN FUNCTION DESCRIPTION Pin No. Pin No. Pin TSOP5 XDFN4 Name Description 1 4 IN Input voltage supply pin 5 1 OUT Regulated output voltage. The output should be bypassed with small 1 F ceramic capacitor. 3 3 EN Chip enable: Applying V < 0.4 V disables the regulator, Pulling V > 1.2 V enables the LDO. EN EN 2 2 GND Common ground connection 4 N/C Not connected. This pin can be tied to ground to improve thermal dissipation. EP EPAD Exposed Pad. Exposed pad can be tied to ground plane for better power dissipation. www.onsemi.com 2