NCV8851-1 Automotive Grade Synchronous Buck Controller The NCV88511 is an adjustable output, synchronous buck controller, which drives dual Nchannel MOSFETs, ideal for high www.onsemi.com power applications. Average current mode control is employed for very fast transient response and tight regulation over wide input voltage and output load ranges. The IC incorporates an internal fixed 6.0 V lowdropout linear regulator (LDO), which supplies charge to the switch mode power supplys (SMPS) bottom gate driver, limiting the power lost to excess gate drive. The IC is designed for operation over a wide input voltage range (4.5 V to 40 V) and is capable of 10 to TSSOP20 SUFFIX DB 1 voltage conversion at 500 kHz. CASE 948E Additional controller features include undervoltage lockout, internal softstart, low quiescent current sleep mode, programmable frequency, SYNC function, average current limiting, cyclebycycle MARKING DIAGRAM overcurrent protection and thermal shutdown. Features V88 Average Current Mode Control 511 ALYW 0.8 V 2% Reference Voltage Wide Input Voltage Range of 4.5 V to 40 V Operates through Load Dump Conditions V88511 = Specific Device Code 6.0 V Lowdropout Linear Regulator (LDO) A = Assembly Location Input UVLO (Undervoltage Lockout) L = Wafer Lot Y = Year Internal Softstart W = Work Week 1.0 A Maximum Quiescent Current in Sleep Mode = PbFree Package Adaptive Nonoverlap Circuitry (Note: Microdot may be in either location) 180 ns Minimum Highside Gate Offtime Programmable Fixed Frequency 170 kHz to 500 kHz ORDERING INFORMATION External Clock Synchronization up to 600 kHz Device Package Shipping Average Current Limiting (ACL) NCV88511DBR2G TSSOP20 2500 / Tape & CyclebyCycle Overcurrent Protection (OCP) (PbFree) Reel Thermal Shutdown (TSD) For information on tape and reel specifications, This is a PbFree Device including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Applications Brochure, BRD8011/D. Automotive Systems Requiring High Current Preregulated Supply for Lowvoltage SMPSs and LDOs Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: November, 2014 Rev. 2 NCV88511/DNCV88511 V 12 9 6V IN OUT LDO I LIMIT Enable TSD Fault EN 11 Logic LDO UVLO + Enable V 3 IN IC Fault V REF FixedFrequency Soft Start 1 SYNC 4 BST Oscillator V SS Ramp Clock R 20 OSC GH 5 Max Duty V 6 SW Q S Min Nonoverlap On Time R Q 6V OUT Reset Dominant PWM 7 GL Fault 8 PGND C 15 COMP OCP BST 2 V IN CS V OCP CEA + 19 CSP CSA C FB 16 18 CSN V 17 REF CS + V OUT + ACL V VEA 14 COMP V SS ACL 10 AGND 13 V FB V CLAMP Figure 1. Functional Block Diagram V IN V 6V IN OUT + 12 9 EN 11 D + BST V V IN IN IC BST 3 4 SYNC Q1 1 GH R OSC C 5 BST 20 + V R SW OSC L 6 Q2 R S + C GL 7 V OUT PGND 8 V IN CS 2 C COMP 15 CSP 19 CSN R C F1 C1 18 C C2 R V C1 FB 13 C FB C V2 16 R V1 R C2 R F0 17 14 C CS V V1 OUT COMP 10 AGND Figure 2. Application Schematic Note: This part is recommended for synchronous use only. www.onsemi.com 2