NCV887301D1R2G ON Semiconductor

DATA SHEET www.onsemi.com Automotive Grade 8 Non-Synchronous Boost 1 Controller SOIC8 D SUFFIX CASE 751 NCV8873 MARKING DIAGRAM The NCV8873 is an adjustable output nonsynchronous boost controller which drives an external Nchannel MOSFET. The device uses peak current mode control with internal slope compensation. The 8 IC incorporates an internal regulator that supplies charge to the gate 8873xxG ALYW driver. Protection features include internallyset softstart, undervoltage 1 lockout, cyclebycycle current limiting and thermal shutdown. Additional features include low quiescent current sleep mode and 8873xxG= Specific Device Code externallysynchronizable switching frequency. xx = 02 A = Assembly Location Features L = Wafer Lot Y = Year Peak Current Mode Control with Internal Slope Compensation W = Work Week 0.2 V 3% Reference Voltage for Constant Current Loads = PbFree Package Fixed Frequency Operation Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump PIN CONNECTIONS Input Undervoltage Lockout (UVLO) EN/SYNC 1 8 VFB Internal SoftStart Low Quiescent Current in Sleep Mode 2 7 ISNS VC CyclebyCycle Current Limit Protection GND 3 VIN 6 Thermal Shutdown (TSD) GDRV 4 VDRV 5 This is a PbFree Device NCV Prefix for Automotive and Other Applications Requiring (Top View) Unique Site and Control Change Requirements AECQ100 Qualified and PPAP Capable ORDERING INFORMATION Package Device Shipping SOIC8 2500 / Tape & NCV887302D1R2G (PbFree) Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: November, 2021 Rev. 11 NCV8873/DNCV8873 V g VIN 6 C g TEMP L VDRV C DRV FAULT MURA110T3G VDRV LOGIC 5 V o CLK EN/ EN/SYNC OSC GDRV Q 1 DRIVE C SYNC 4 D2 o LOGIC SC NVTFS5826NL ISNS 2 VC CL CSA R SNS 7 GND Dn 3 + R C VFB 8 Gm C R C F1 SS V ref Figure 1. Simplified Block Diagram and Example Application Schematic PACKAGE PIN DESCRIPTIONS Pin Symbol Pin No. Function 1 EN/SYNC Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable timeout period. 2 ISNS Current sense input. Connect this pin to the source of the external NMOSFET, through a currentsense resistor to ground to sense the switching current for regulation and current limiting. 3 GND Ground reference. 4 GDRV Gate driver output. Connect to gate of the external N MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. 5 VDRV Driving voltage. Internally regulated supply for driving the external N MOSFET, sourced from VIN. Bypass with a 1.0 F ceramic capacitor to ground. 6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi- tion to a diode from the output voltage to VDRV and/or VIN. 7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. 8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. www.onsemi.com 2 PWM