NLV74HC589ADTR2G ON Semiconductor

MC74HC589A 8-Bit Serial or Parallel-Input/Serial-Output Shift Register with 3-State Output MC74HC589A MAXIMUM RATINGS Symbol Parameter Value Unit V DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V CC V DC Input Voltage (Referenced to GND) 0.5 V + 0.5 V in CC V DC Output Voltage (Referenced to GND) 0.5 V + 0.5 V out CC I DC Input Current, per Pin 20 mA in I DC Output Current, per Pin 35 mA out I DC Supply Current, V and GND Pins 75 mA CC CC I DC Ground Current per Ground Pin 75 mA GND T Storage Temperature Range 65 to +150 C STG T Lead Temperature, 1 mm from Case for 10 Seconds 260 C L T Junction Temperature Under Bias +150 C J Thermal Resistance PDIP 78 C/W JA SOIC 112 TSSOP 148 P Power Dissipation in Still Air at 85 C PDIP 750 mW D SOIC 500 450 TSSOP MSL Moisture Sensitivity Level 1 F Flammability Rating Oxygen Index: 30% 35% UL 94 V0 0.125 in R V ESD Withstand Voltage Human Body Model (Note 1) > 4000 V ESD Machine Model (Note 2) > 200 Charged Device Model (Note 3) > 1000 I Latchup Performance Above V and Below GND at 85 C (Note 4) 300 mA Latchup CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22A114A. 2. Tested to EIA/JESD22A115A. 3. Tested to JESD22C101A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 2.0 6.0 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V in out CC T Operating Temperature, All Package Types 55 125 C A t , t Input Rise and Fall Time V = 2.0 V 0 1000 ns r f CC V = 3.0 V 0 800 CC (Figure 2) V = 4.5 V 0 500 CC V = 6.0 V 400 CC Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. Unused inputs may not be left open. All inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.