NLV74HCT14ADR2G ON Semiconductor

MC74HCT14A Hex Schmitt-Trigger Inverter with LSTTL Compatible Inputs HighPerformance SiliconGate CMOS MC74HCT14A MAXIMUM RATINGS Symbol Parameter Value Unit V DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V CC V DC Input Voltage (Referenced to GND) 0.5 to V + 0.5 V I CC V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V O CC I DC Input Diode Current 20 mA IK I DC Output Diode Current 25 mA OK I DC Output Sink Current 25 mA O I DC Supply Current per Supply Pin 50 mA CC I DC Ground Current per Ground Pin 50 mA GND T Storage Temperature Range 65 to +150 C STG T Lead Temperature, 1 mm from Case for 10 Seconds 260 C L T Junction Temperature under Bias +150 C J Thermal Resistance SOIC 125 C/W JA TSSOP 170 P 500 mW Power Dissipation in Still Air at 85 C SOIC D TSSOP 450 MSL Moisture Sensitivity Level 1 F Flammability Rating Oxygen Index: 30% 35% UL 94 V0 0.125 in R V ESD Withstand Voltage Human Body Model (Note 1) > 4000 V ESD Machine Model (Note 2) > 300 Charged Device Model (Note 3) > 1000 I Latchup Performance Above V and Below GND at 85 C (Note 4) 300 mA Latchup CC Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Tested to EIA/JESD22A114A. 2. Tested to EIA/JESD22A115A. 3. Tested to JESD22C101A. 4. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit V DC Supply Voltage (Referenced to GND) 4.5 5.5 V CC V , V DC Input Voltage, Output Voltage (Referenced to GND) 0 V V I O CC T Operating Temperature, All Package Types 55 +125 C A t , t Input Rise and Fall Time (Figure 1) (Note 5) ns r f Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 5. No Limit when V 50% V , I > 1 mA. I CC CC 6. Unused inputs may not be left open. All inputs must be tied to a highlogic voltage level or a lowlogic input voltage level.