NLV74LCX573DTR2G ON Semiconductor

MC74LCX573 Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout With 5 VTolerant Inputs and Outputs MC74LCX573 1 OE 11 LE 19 LE O0 2 Q D0 D V O0 O1 O2 O3 O4 O5 O6 O7 LE CC 20 19 18 17 16 15 14 13 12 11 18 LE O1 3 Q D1 D 17 LE O2 4 Q D2 D 1 2 3 4567 9 8 10 OE D0 D1 D2 D3 D4 D5 D6 D7 GND 16 LE O3 5 Q Figure 1. Pinout (Top View) D3 D 15 LE O4 6 Q PIN NAMES D4 D Pins Function OE Output Enable Input 14 LE O5 7 Q LE Latch Enable Input D5 D D0 D7 Data Inputs O0O7 3State Latch Outputs 13 LE O6 8 Q D6 D 12 LE O7 9 Q D7 D Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE LE Dn On Operating Mode L H H H Transparent (Latch Disabled) Read Latch L H L L L L h H Latched (Latch Enabled) Read Latch L L l L L L X NC Hold Read Latch H L X Z Hold Disabled Outputs H H H Z Transparent (Latch Disabled) Disabled Outputs H H L Z H L h Z Latched (Latch Enabled) Disabled Outputs H L l Z H = High Voltage Level h = High Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition L = Low Voltage Level l = Low Voltage Level One Setup Time Prior to the Latch Enable HightoLow Transition NC = No Change, State Prior to the Latch Enable HightoLow Transition X = High or Low Voltage Level or Transitions are Acceptable Z = High Impedance State For I Reasons DO NOT FLOAT Inputs CC