NLVPCA9535EDTR2G ON Semiconductor

2 I/O Expander for I C Bus with Interrupt, Low-Power, 16-bit PCA9535E, PCA9535EC The PCA9535E and PCA9535EC devices provide 16 bits of General Purpose parallel Input / Output (GPIO) expansion through the www.onsemi.com 2 I Cbus / SMBus. The PCA9535E and PCA9535EC consist of two 8 bit MARKING DIAGRAMS Configuration (Input or Output selection) Input, Output and Polarity Inversion (activeHIGH or activeLOW operation) registers. At power on, all I/Os default to inputs. Each I/O may be configured as PCA9535E(C) either input or output by writing to its corresponding I/O configuration AWLYYWWG SOIC24 bit. The data for each Input or Output is kept in its corresponding Input DW SUFFIX or Output register. The Polarity Inversion register may be used to CASE 751E invert the polarity if the read register. All registers can be read by the system master. The PCA9535E, identical to the PCA9655E but with the internal I/O pull up resistors removed, has greatly reduced power PCA95 consumption when the I/Os are held LOW. 35E(C)G The PCA9535EC is identical to the PCA9535E but with ALYW TSSOP24 highimpedance opendrain outputs at all the I/O pins. DT SUFFIX The PCA9535E and PCA9535EC provide an opendrain interrupt CASE 948H output which is activated when any input state differs from its corresponding input port register state. The interrupt output is used to indicate to the system master that an input state has changed. The PCA 1 poweron reset sets the registers to their default values and initializes 9535E(C) WQFN24 the device state machine. ALYW MT SUFFIX Three hardware pins (AD0, AD1, AD2) are used to configure the CASE 485BG 2 2 I Cbus slave address of the device. The I Cbus slave addresses of the PCA9535E and PCA9535EC are the same as the PCA9655E. This XXXX = Specific Device Code allows up to 64 of these devices in any combination to share the same A = Assembly Location 2 WL, L = Wafer Lot I Cbus/SMBus. YY, Y = Year WW, W = Work Week Features G or = PbFree Package V Operating Range: 1.65 V to 5.5 V DD (Note: Microdot may be in either location) SDA Sink Capability: 30 mA 5.5 V Tolerant I/Os ORDERING INFORMATION Polarity Inversion Register See detailed ordering and shipping information in the package dimensions section on page 17 of this data sheet. Active LOW Interrupt Output Low Standby Current Noise Filter on SCL/SDA Inputs ESD Performance: 3000 V Human Body Model, 400 V Machine Model No Glitch on Powerup NLV Prefix for Automotive and Other Applications Internal Poweron Reset Requiring Unique Site and Control Change 64 Programmable Slave Addresses using Three Requirements AECQ100 Qualified and PPAP Address Pins Capable 16 I/O Pins which Default to 16 Inputs These are PbFree Devices 2 I C SCL Clock Frequencies Supported: Standard Mode: 100 kHz Fast Mode: 400 kHz Fast Mode +: 1 MHz Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: November, 2019 Rev. 8 PCA9535E/DPCA9535E, PCA9535EC BLOCK DIAGRAM PCA9535E IO1 0 PCA9535EC IO1 1 8bit IO1 2 AD0 INPUT/ IO1 3 AD1 OUTPUT IO1 4 AD2 PORTS write pulse IO1 5 IO1 6 read pulse IO1 7 2 I CBUS/SMBus CONTROL SCL IO0 0 INPUT IO0 1 FILTER SDA 8bit IO0 2 INPUT/ IO0 3 OUTPUT IO0 4 PORTS write pulse IO0 5 IO0 6 read pulse V IO0 7 DD POWERON RESET V SS V DD LP filter INT Remark: All I/Os are set as inputs at reset. Figure 1. Block Diagram data from output port shift register register data configuration (1) register V DD data from Q1 DQ shift register FF write DQ configuration CK Q pulse FF I/O pin Q2 write pulse CK V input port SS output port register register DQ input port register data FF read pulse CK to INT polarity inversion register data from polarity DQ shift register inversion FF register data write polarity CK pulse At poweron reset, all registers return to default values. 1. PCA9535EC I/Os are open drain only. The portion of the PCA9535E schematic marked inside the dotted line box is not in PCA9535EC. Figure 2. Simplified Schematic of I/Os www.onsemi.com 2