SA572DG ON Semiconductor

DATA SHEET www.onsemi.com Programmable Analog Compandor 16 1 SA572 SOIC16 WB D SUFFIX The SA572 is a dual-channel, high-performance gain control CASE 751G circuit in which either channel may be used for dynamic range compression or expansion. Each channel has a full-wave rectifier to MARKING DIAGRAM detect the average value of input signal, a linearized, temperature- compensated variable gain cell ( G) and a dynamic time constant buffer. The buffer permits independent control of dynamic attack and 16 recovery time with minimum external components and improved low frequency gain control ripple distortion over previous compandors. SA572D The SA572 is intended for noise reduction in high-performance AWLYYWWG audio systems. It can also be used in a wide range of communication systems and video recording applications. 1 Features Independent Control of Attack and Recovery Time A = Assembly Location Improved Low Frequency Gain Control Ripple WL = Wafer Lot Complementary Gain Compression and Expansion with YY = Year WW = Work Week External Op Amp = PbFree Package Wide Dynamic Range Greater than 110 dB (Note: Microdot may be in either location) Temperature-Compensated Gain Control Low Distortion Gain Cell Low Noise 6.0 V Typical PIN CONNECTIONS Wide Supply Voltage Range 6.0 V-22 V 16 V TRACK TRIM A 1 CC System Level Adjustable with External Components 2 RECOV. CAP A 15 TRACK TRIM B This is a PbFree Device* 14 RECT. IN A 3 RECOV. CAP B 4 13 Applications ATTACK CAP A RECT. IN B G OUT A 12 5 ATTACK CAP B Dynamic Noise Reduction System THD TRIM A 6 11 G OUT B Voltage Control Amplifier G IN A 7 10 THD TRIM B Stereo Expandor 8 9 GND G IN B Automatic Level Control High-Level Limiter Low-Level Noise Gate ORDERING INFORMATION State Variable Filter See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. *For additional information on our PbFree strategy and soldering details, please download the onsemi Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: October, 2021 Rev. 3 SA572/DSA572 R 1 (5,11) (7,9) 6.8k (6,10) G 500 GAIN CELL (1,15) (3,13) + + 10k BUFFER 270 10k RECTIFIER (16) P.S. (8) (4,12) (2,14) Figure 1. Block Diagram PIN FUNCTION DESCRIPTION Pin Symbol Description 1 TRACK TRIM A Tracking Trim A 2 RECOV. CAP A Recovery Capacitor A 3 RECT. IN A Rectifier A Input 4 ATTACK CAP A Attack Capacitor A 5 G OUT A Variable Gain Cell A Output 6 THD TRIM A Total Harmonic Distortion Trim A 7 G IN A Variable Gain Cell A Input 8 GND Ground 9 G IN B Variable Gain Cell B Input 10 THD TRIM B Total Harmonic Distortion Trim B 11 G OUT B Variable Gain Cell B Output 12 ATTACK CAP B Attack Capacitor B 13 RECT. IN B Rectifier B Input 14 RECOV. CAP B Recovery Capacitor B 15 TRACK TRIM B Tracking Trim B 16 V Positive Power Supply CC www.onsemi.com 2