MN101EFA6/A5/A1/A0 Series 8-bit Single-chip Microcontroller PubNo. 216A6-012E 1.1 Overview 1.1.1 Overview The MN101E series of 8-bit single-chip microcomputers (the memory expansion version of MN101C series) incorporate multiple types of peripheral functions. This chip series is well suited for automotive power window, camera, TV, CD, printer, telephone, home appliance, PPC, fax machine, music instrument and other applications. This LSI brings to embedded microcomputer applications flexible, optimized hardware configurations and a sim- ple efficient instruction set. MN101EFA6/A5/A1/A0 has an internal 32 KB of ROM and 1 KB of RAM. Periph- eral functions include 5 external interrupts, including NMI, 8 timer counters, 3 (MN101EFA5/A0: 2) types of serial interfaces, A/D converter, watchdog timer and buzzer output (MN101EFA5/A0: no buzzer). The system configuration is suitable for system control microcontroller. With 2 oscillation systems (internal frequency: 16 MHz, crystal/ceramic frequency: max. 10 MHz) contained on the chip, the system clock can be switched to high-speed frequency input (NORMAL mode) or PLL input (PLL mode). The system clock is generated by dividing the oscillation clock or PLL clock. The best operation clock for the system can be selected by switching its frequency ratio by programming. High speed mode has NORMAL mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and PLL), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll. A machine cycle (minimum instruction execution time) in NORMAL mode is 200 ns when the original oscillation fosc is 10 MHz (PLL is not used). A machine cycle in the double speed mode, in which the CPU operates on the same clock as the external clock, is 100 ns when fosc is 10 MHz. A machine cycle in the PLL mode is 50 ns (max- imum). 1.1.2 Product Summary This manual describes the following model. Table:1.1.1 Product Summary Capacitive Touch Model ROM Size RAM Size Classification Package Detection Circuit MN101EFA6A 32 KB 1 KB Flash EEPROM version 44-Pin QFP 48-Pin TQFP MN101EFA1A 32 KB 1 KB Flash EEPROM version - MN101EFA5A 32 KB 1 KB Flash EEPROM version 32-Pin SSOP 32-Pin TQFP MN101EFA0A 32 KB 1 KB Flash EEPROM version - Publication date: November 2014 MN101EFA6/A5/A1/A0 Series 8-bit Single-chip Microcontroller PubNo. 216A6-012E 1.2 Hardware Functions Feature - ROM capacity: 32 KB - RAM capacity: 1 KB - Package: MN101EFA6/A1 44-Pin QFP (10 mm 10 mm / 0.8 mm pitch) 48-Pin TQFP (7 mm 7 mm / 0.5 mm pitch) MN101EFA5/A0 32-Pin TQFP (7 mm 7 mm / 0.8mm pitch) 32-Pin SSOP (6.1 mm 11 mm / 0.65mm pitch, halogen free) Panasonichalogen fre semiconductor products refer to the products made of molding resin and interposer which conform to the following standards. - Bromine : 900 ppm (Maximum Concentration Value) - Chlorine : 900 ppm (Maximum Concentration Value) - Bromine + Chlorine : 1500 ppm (Maximum Concentration Value) The above-mentioned standards are based on the numerical value described in IEC61249-2-21. Antimony and its compounds are not added intentionally. - Machine Cycle: 0.05 s / fs: 20 MHz (4.0 V to 5.5 V) - Oscillation circuit: 2 channel oscillation circuit Internal oscillation (frc): 16 MHz Crystal/ceramic (fosc): Maximum 10 MHz -Clock Multiplication circuit (PLL Circuit) PLL circuit output clock (fpll): fosc multiplied by 2, 3, 4, 5, 6, 8, 10, 1/2 frc multiplication by 4, 5 enable -Clock Gear for System Clock System Clock (fs): fpll divided by 1, 2, 4, 16, 32, 64, 128 -Clock Gear for control clock of peripheral function Control clock of peripheral function (fpll-div): stop or fpll divided by 1, 2, 4, 8, 16 - Operation Mode: NORMAL mode HALT mode STOP mode (The operation clock can be switched in each mode.) - Operating Voltage: 4.0 V to 5.5 V Publication date: November 2014