MN101LR05D/04D/03D/02D 8-bit Single-chip Microcontroller PubNo. 21705-019E 1.1 Product Summary This LSI user s manual describes MN101LR05D/04D/03D/02D. The detail of product specification is described mainly about MN101LR05D. For the difference between each product, See 1.3 Comparison of Product Specification and 1.4.1 Pin Configu- ration . V voltage after reset release, oscillation stabilization wait time after reset release and ROM capacity vary DD18 depending on the ROM name of each product. Table: 1.1.1 shows the difference of specifications between the ROM name. Table:1.1.1 Product Summary Product Name ROM name * V voltage after Oscillation stabiliza- ROM (ReRAM) capacity DD18 tion wait time after (Program area/Data area) reset release reset release 11 MN101LR05D XW 1.1 V 62 KB / 2 KB 2 /(f /2) SRC MN101LR04D XX 59 KB / 4 KB MN101LR03D MN101LR02D XY 53 KB / 8 KB XZ 41 KB / 16 KB 8 XA 1.8 V 62 KB / 2 KB 2 /(f /2) SRC XB 59 KB / 4 KB XC 53 KB / 8 KB XD 41 KB / 16 KB * ROM name: XA/XB/XC/XD/XW/XX/XY/XZ indicates the product that ReRAM is blank. When using the debugger or programmer, setProduct name + ROM nam (e.g.: MN101LR05DXA/XW) in the fieldProduct typ orMicrocomputer product typ. WhenROM nam is set incorrectly, connect error is occurred. When nothing is set toROM nam, XA/XW is selected. (e.g.: MN101LR05D MN101LR05DXA/XW) .. Publication date: October 2014 MN101LR05D/04D/03D/02D 8-bit Single-chip Microcontroller PubNo. 21705-019E 1.2 Hardware Features Features In this document, the divided clock and the frequency of it are described as follows: Divided clock:Clock name/n (n: division ratio) Frequency: f Clock name CPU Core - AM13L core - LOAD-STORE architecture (3- or 4-stage Pipeline) Machine Cycle and Operating Voltage - High-Speed mode 100 ns / 10 MHz (Max) (V : 1.8 V to 3.6 V) DD30 1.0 s / 1 MHz (Max) (V : 1.3 V to 3.6 V) DD30 - Low-Speed Mode 25 s / 40 kHz (Max) (V : 1.1 V to 3.6 V) DD30 Operating Mode - NORMAL mode (High-Speed mode) - SLOW mode (Low-Speed mode) - HALT mode (High-Speed/Low-Speed mode) - STOP mode Embedded Memory - ROM (ReRAM): 64 KB (Programmable area and Data area vary depending on the ROM name. For details, see Table:1.1.1.) - RAM: 4 KB ReRAM Specification - Program voltage (V ): 1.8 V to 3.6 V DD30 - Program cycles: 1000 times (Program area), 100000 times (Data area) - Data is rewritable in bytes without data erase. Clock Oscillator (4 circuits) - External Low-Speed Oscillation (SOSCCLK): 32.768 kHz (crystal or ceramic) - External High-Speed Oscillation (HOSCCLK): up to 10 MHz (crystal or ceramic) - Internal Low-Speed Oscillation (SRCCLK): 40 kHz 20 % (V : 1.1 V to 3.6 V) DD30 - Internal High-Speed Oscillation (HRCCLK): 10/8 MHz 3 % (V : 1.8 V to 3.6 V) DD30 1 MHz 10 % (V : 1.3 V to 3.6 V) DD30 * MN101LR02D does not have external high-speed oscillation (HOSCCLK). Internal Operating Clock - System Clock (SYSCLK): 10 MHz (Max) SYSCLK is generated by dividing HCLK or SCLK, and the division ratio is 1, 2, 4, 8, 16 or 32. HCLK: HOSCCLK or HRCCLK SCLK: SOSCCLK or SRCCLK * MN101LR02D cannot be selected HOSCCLK. Publication date: October 2014