DS1302 DS1302 Trickle Charge Timekeeping Chip FEATURES PIN ASSIGNMENT Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with V 1 8 V CC2 CC1 leap year compensation valid up to 2100 X1 2 7 SCLK X2 3 6 I/O 31 x 8 RAM for scratchpad data storage GND 4 5 RST Serial I/O for minimum pin count DS1302 8PIN DIP (300 MIL) 2.05.5 volt full operation V 1 8 V CC2 CC1 Uses less than 300 nA at 2.0 volts X1 2 7 SCLK X2 3 6 I/O Singlebyte or multiplebyte (burst mode) data trans- GND 4 5 RST fer for read or write of clock or RAM data DS1302S 8PIN SOIC (200 MIL) DS1302Z 8PIN SOIC (150 MIL) 8pin DIP or optional 8pin SOICs for surface mount Simple 3wire interface PIN DESCRIPTION X1, X2 32.768 kHz Crystal Pins TTLcompatible (V = 5V) CC GND Ground Optional industrial temperature range 40C to +85C RST Reset I/O Data Input/Output DS1202 compatible SCLK Serial Clock Added features over DS1202 V , V Power Supply Pins CC1 CC2 Optional trickle charge capability to V CC1 Dual power supply pins for primary and backup ORDERING INFORMATION power supplies PART DESCRIPTION Backup power supply pin can be used for battery DS1302 Serial Timekeeping Chip 8pin DIP or super cap input DS1302S Serial Timekeeping Chip Additional scratchpad memory (7 bytes) 8pin SOIC (200 mil) DS1302Z Serial Timekeeping Chip 8pin SOIC (150 mil) DESCRIPTION The DS1302 Trickle Charge Timekeeping Chip contains Interfacing the DS1302 with a microprocessor is simpli- a real time clock/calendar and 31 bytes of static RAM. It fied by using synchronous serial communication. Only communicates with a microprocessor via a simple serial three wires are required to communicate with the clock/ interface. The real time clock/calendar provides RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK seconds, minutes, hours, day, date, month, and year (Serial clock). Data can be transferred to and from the information. The end of the month date is automatically clock/RAM one byte at a time or in a burst of up to 31 adjusted for months with less than 31 days, including bytes. The DS1302 is designed to operate on very low corrections for leap year. The clock operates in either power and retain data and clock information on less the 24hour or 12hour format with an AM/PM indicator. than 1 microwatt. 032598 1/12DS1302 The DS1302 is the successor to the DS1202. In addi- After the first eight clock cycles have loaded the com- tion to the basic timekeeping functions of the DS1202, mand word into the shift register, additional clocks will the DS1302 has the additional features of dual power output data for a read or input data for a write. The num- pins for primary and backup power supplies, program- ber of clock pulses equals eight plus eight for byte mode mable trickle charger for V , and seven additional or eight plus up to 248 for burst mode. CC1 bytes of scratchpad memory. COMMAND BYTE The command byte is shown in Figure 2. Each data OPERATION The main elements of the Serial Timekeeper are shown transfer is initiated by a command byte. The MSB (Bit 7) in Figure 1: shift register, control logic, oscillator, real must be a logic 1. If it is zero, writes to the DS1302 will time clock, and RAM. To initiate any transfer of data, be disabled. Bit 6 specifies clock/calendar data if logic RST is taken high and eight bits are loaded into the shift 0 or RAM data if logic 1. Bits one through five specify register providing both address and command informa- the designated registers to be input or output, and the tion. Data is serially input on the rising edge of the SCLK. LSB (Bit 0) specifies a write operation (input) if logic 0 The first eight bits specify which of 40 bytes will be or read operation (output) if logic 1. The command accessed, whether a read or write cycle will take place, byte is always input starting with the LSB (Bit 0). and whether a byte or burst mode transfer is to occur. DS1302 BLOCK DIAGRAM Figure 1 V CC1 32.768 kHz POWER V CC2 CONTROL GND X1 X2 I/O OSCILLATOR REAL TIME AND DIVIDER CLOCK INPUT SHIFT DATA BUS REGISTERS SCLK RST COMMAND AND 31 X 8 RAM ADDRESS BUS CONTROL LOGIC ADDRESS/COMMAND BYTE Figure 2 7 6 5 4 3 2 1 0 RAM RD 1 A4 A3 A2 A1 A0 CK W 032598 2/12