PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports Highlights Highlights The ExpressLane PEX 8732 device ofThe ExpressLane PEX 8732 device offers Multi-Host PCI Express fers Multi-Host PCI Express switchingswitching capability en capability enabling usabling usersers to to connect multiple hos connect multiple hosts tots to their their PEPEXX 8732 Ge8732 General Feneral Featureatures s oo 32-lane, 8-por32-lane, 8-port Pt PCCIe GenIe Gen 3 switch 3 switch respective endpoints via scalablrespective endpoints via scalable, high bandwidth, non-blocking e, high bandwidth, non-blocking -- IntegrateIntegratedd 8.0 8.0 GT/s SerDes GT/s SerDes 22 interconnection to a wide variety of applications including interconnection to a wide variety of applications including servers,servers, oo 27 x 27mm27 x 27mm , 67, 676-pin FCBGA packag6-pin FCBGA package e oo TyTyppiical Power: cal Power: 6.0 Watts 6.0 Watts storage, communications, storage, communications, and graphics platforms.and graphics platforms. The P The PEX 8732 is EX 8732 is well suited for well suited for fan-outfan-out, , aggregationaggregation,, and peer-to-peer and peer-to-peer traffic patterns. traffic patterns. PE PEXX 8738732 Key2 Key Fea Feattuures res oo SSttaandarndardds Compliant s Compliant Multi-Host Architecture Multi-Host Architecture -- PCI Express BasPCI Express Basee Specification, r Specification, r3.0 3.0 The PEX 873The PEX 8732 em2 employploys an s an enhanced version of PLXenhanced version of PLXs field tested PEX 8632 s field tested PEX 8632 (compatible w/ (compatible w/ PCIe r1.0a/1.1PCIe r1.0a/1.1 & 2.0& 2.0)) PCIe switch aPCIe switch architecture, wrchitecture, whhich allows users to configure the device in legacyich allows users to configure the device in legacy -- PCI Power Management SpPCI Power Management Spec, rec, r1.21.2 -- Microsoft Vista Microsoft Vista Compliant Compliant single-host mode or msingle-host mode or muulti-host mlti-host mode wiode with th up tup too six six host ports capable of 1+1 host ports capable of 1+1 -- Supports Access ControlSupports Access Control Serv Serviciceess (one active & one backup) (one active & one backup) or N+1 (N acor N+1 (N active & one backup) host faitive & one backup) host failover. This lover. This -- DDyynamic link-width connamic link-width conttrol rol powerful architectural enhancepowerful architectural enhancemment enabent enablles users to build PCIe based syes users to build PCIe based systemstems s -- DDyynamnamiicc S SeerDesrDes s sppeed eed controcontroll to support hito support high-availabilitgh-availabilityy,, failover, failover, redundant, redundant, or clustered syor clustered systems. stems. oo HHiighgh P Perforerformamannce ce pperformanceerformancePAPAK K 9 9 Read PaRead Pacicingng (ba (bandwidth throndwidth throttlttlining) g) High Performance & LowHigh Performance & Low Packet Packet LatencLatencyy 9 9 MulticastMulticast The PEX 873The PEX 8732 architecture supports pac2 architecture supports packket et cut-thru with a maximum cut-thru with a maximum 9 9 DDyynamic Buffernamic Buffer//FC CrediFC Credit Pool t Pool latency of 10latency of 106ns (x8 to 6ns (x8 to x8x8).). This, com This, combbined with large packet ined with large packet mmeemorymory, , -- Non-blocking sNon-blocking swwitch fitch faabrbric ic flexible commflexible common buffer/FC credit pool on buffer/FC credit pool and non-and non-blocblocking iking innternal switch ternal switch -- Full linFull line re raattee on on allall ports ports -- Packet Cut-ThruPacket Cut-Thru w with 106ns maxith 106ns max pack packet et architecture, architecture, provides full provides full line rate on all ports for perline rate on all ports for perfformance-huormance-hungrngryy llatateencncy (x8y (x8 to to x8 x8) ) applications such as applications such as serveserverrss andand switch switch fabricsfabrics. The low latency. The low latency enables enables -- 2KB Max Pay2KB Max Payllooaad Sized Size applications to achieve higapplications to achieve highh thro throughughputput and performand performance. In additiance. In addition to lon to loow w oo FlexiblFlexiblee Config Configuration uration latencylatency, the , the ddeevice supports a packet payvice supports a packet paylload size of up to oad size of up to 2042048 b8 byytes, tes, -- Ports configurabPorts configurable le as x1, x2, x4, as x1, x2, x4, x8, x1x8, x166 enabling the enabling the user to achieveuser to achieve even higher even higher throu throughpghput.ut. -- Registers Registers configconfigurable withurable with strap strappping ing 22 pins, EEPROM, pins, EEPROM, II C, orC, or hos host software t software -- Lane andLane and polar polarityity reversreversal al Data IntegrityData Integrity -- ComComppatibleatible with with PCIe 1 PCIe 1..0a PM0a PM The PEX 873The PEX 8732 prov2 providesides end-to-end CRC end-to-end CRC (ECRC) pr (ECRC) protection and otection and PoisonPoison bit bit oo MMuulti-Host & Fail-Overlti-Host & Fail-Over Suppor Supportt support tsupport too en enable designs that require able designs that require end-to-end data integrityend-to-end data integrity. PLX also . PLX also -- Configurable NoConfigurable Non-Trann-Transparensparent (t (NNT) port T) port -- FailoverFailover with N with NTT port port supports data supports data path paritpath parityy an and md meemomoryry (RAM) error correction circuitry (RAM) error correction circuitry -- Up to 6Up to 6 upstream/Host ports with 1+1 or upstream/Host ports with 1+1 or throughoutthroughout the internal data path the internal data paths as packets pass through ts as packets pass through thhe switch. e switch. N+1 failoverN+1 failover to to other upsother upstrtream peam ports orts oo QQuualitality ofy of S Serviervice (ce (QoSQoS) ) Flexible Configuration Flexible Configuration -- Eight traffEight traffiic clasc classes per porses per port t The PEX 8The PEX 8732732s 8s 8 por ports can be ts can be -- Weighted rouWeighted round-nd-robin source robin source x4x4 x8x8 pport arbort arbitraitrationtion configured toconfigured to lane widths lane widths of x1, x2,of x1, x2, oo RReliabiliteliability, Avy, Avaailabilitilability, Sey, Servicrviceabiliteabilityy x4, xx4, x88, or, or x16. F x16. Fllexiexibble buffer le buffer vvisisiiononPAKPAK allocation, along with thallocation, along with the device s e device s PPEEXX 8732 8732 PPEEXX 8732 8732 99 Per Port PerformPer Port Performance Monitoringance Monitoring flexible packet flowflexible packet flow control, control, Per port pPer port paayyllooaadd & & h headeader er counters counters maximmaximiizes throuzes througghhput forput for 99 SeSerDerDes Eys Eye Cae Capture pture 3 x43 x4 8x8x22 3 x3 x88 99 PCIe Packet GeneratorPCIe Packet Generator applications where applications where more trafficmore traffic 9 9 Error Injection Error Injection and Loopbackand Loopback x1x166 flows in the downstreamflows in the downstream,, rather than rather than x8x8 -- 3 Hot Plug Ports3 Hot Plug Ports with n with naativtive HP e HP SigSignals nals upstreamupstream, direction. Any, direction. Any p poort can be rt can be 22 -- All ports hoAll ports hot pt plluugg cap capablablee thru thru I I C C designated as the upstreamdesignated as the upstream port, port, (Hot Plug Contr(Hot Plug Controollerller on on evereveryy poport) rt) PPEEXX 8732 8732 PPEEXX 8732 8732 which can be changed dwhich can be changed dyynnaammicallyically.. -- ECRC andECRC and Poison Poison bit support bit support -- Data PaData Path pth paaritrityy Figure 1 shows soFigure 1 shows some ofme of the PEX the PEX -- MemoryMemory (RAM) Error (RAM) Error Correctio Correction n 87328732s coms commmon port configurationson port configurations x8x8 x8x8 1010 x x22 -- INTA and FATAL ERR sINTA and FATAL ERR signals ignals . FiguFigurree 11.. C Coommmmoon n PPoorrtt C Coonfnfiguriguraattionionss in legacyin legacy Si Single-Host ngle-Host mmodeode -- Advanced ErrorAdvanced Error Reporting Reporting -- PPoort Srt Sttatusatus b bitsits a and GPnd GPIO avIO avaiailablabllee Per port Per port errorerror diagnostics diagnostics -- JTAG AC/DC boundarJTAG AC/DC boundaryy scan scan PLX Technolo PLX Technologgyy, , www.plxtech.www.plxtech.com com Page 1 of 5Page 1 of 5 10/7/2010, Ve10/7/2010, Version 1.0rsion 1.0 PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports PEX 8732, PCI Express Gen 3 Switch, 32 Lanes, 8 Ports The PEX 8732 can also be configured in Multi-Host mThe PEX 8732 can also be configured in Multi-Host modeode Multi-Host & Failover Support Multi-Host & Failover Support where users where users can choose up can choose up to six ports asto six ports as host/upstream host/upstream In Multi-HostIn Multi-Host m mode, PEX ode, PEX 8732 can be configured wit8732 can be configured withh up up ports and assign a desired numports and assign a desired numbber of downstreaer of downstream portm ports to s to to six upstreamto six upstream host ports, each with its own dedicated host ports, each with its own dedicated each host. In each host. In Multi-Host mode, a virtual Multi-Host mode, a virtual switchswitch is cre is creaated ted downstreamdownstream ports. The deports. The device can be configured fvice can be configured foor r 1+1 1+1 for each host port and its asfor each host port and its associated downstreasociated downstreamm ports ports redundancredundancyy o orr N+1 redund N+1 redundancyancy. T. Thhe PEX 8732 allowe PEX 8732 allowss th the e inside the device. The traffiinside the device. The traffic between thec between the port ports of a virtual s of a virtual hosts to commhosts to communicunicaate theite their status to eacr status to each other via special h other via special sswitch is cowitch is completelympletely isolate isolatedd from from the traffic in other the traffic in other door-bell regidoor-bell registers. In failover sters. In failover mmode, if a host fails, thode, if a host fails, the e virtual switches. Figure 2 ilvirtual switches. Figure 2 illustrates solustrates some configuratiome configurations ns host designathost designateed for failoved for failover will disable the upstreamr will disable the upstream poport rt of the PEX 8732 iof the PEX 8732 inn Multi- Multi-Host Host mmode where each elliode where each ellipse pse attached to the failing host attached to the failing host and programand program the downstream the downstream representsrepresents a v a viirtual switch inside the device. rtual switch inside the device. ports of thatports of that hhoost to its ownst to its own dom domain. Figure 4a shows a two ain. Figure 4a shows a two host shost syystemstem in Multi-Host in Multi-Host mmode ode with two virtual switwith two virtual switches ches The PEX 8732 aThe PEX 8732 also provides severlso provides several wayal wayss t too config configurure its e its inside the devinside the device and Figurice and Figure 4b shows Host 1 disablede 4b shows Host 1 disabled registers. The dregisters. The device can be configured tevice can be configured thhrougrough strapph strapping ing after failure and Host 2 after failure and Host 2 having taken having taken ovover all of Host 1s er all of Host 1s 22 pins, pins, II C C end-points.end-points. 4 x44 x4ss 22 x8s x8s interfaceinterface, host , host HoHosstt 1 1 HosHostt 2 2 HosHostt 1 1 Host 2 software, or an software, or an optional serialoptional serial PPEEXX 8732 8732 PPEEXX 8732 8732 PEX 8732PEX 8732 PEX 8732PEX 8732 EEPROEEPROM. This M. This allows for easallows for easy y 8 x28 x2ss 44 x4sx4s debug ddebug duurinringg the the EnEnd d EnEnd d EnEnd d EnEnd d EEnd nd End End End x8 &x8 & 33 x4sx4s developmdevelopmenent t PoPoiinntt PoPoiinntt PoPoiinntt PoPoiinntt PoPoint Point Point Point 2 x22 x2ss FigurFigure 4e 4aa MMuultlti-i-HHoosstt FiFigurgure e 44bb.. M Muultlti-i-HHoosstt Fail Fail-O-Ovveerr phase, phase, performance performance PPEEXX 8732 8732 PPEEXX 8732 8732 mmonitoring onitoring Hot Plug for High Availability dduring the uring the Hot plug capability allows users to replace hardware 2x42x4ss operation phase, operation phase, modules and perform maintenance without powering down & 6& 6 x2x2ss 44 x4sx4s & & 2 2 x2sx2s and driver or and driver or the system. The PEX 8732 hot plug capability feature FigurFiguree 22.. MMultulti-i-HHosostt P Porortt C Confonfiguriguraattionsions software upgrade. software upgrade. makes it suitable for High Availability (HA) applications. Three downstream ports include a Standard Dual-Host & FailovDual-Host & Failover Support er Support Hot Plug Controller. If the PEX 8732 is used in an In Single-HoIn Single-Host st mmode, ode, the PEX 8732 suthe PEX 8732 supports a pports a Non-Non- application where one or more of its downstream ports TransparentTransparent (NT) Port, (NT) Port, which enables the which enables the connect to PCI Express slots, each ports Hot Plug imimplemplementation of entation of Controller can be used to manage the hot-plug event of its dual-host systemsdual-host systems for for associated slot. Every port on the PEX 8732 is equipped PPrriimmary Hary Hoostst SSecoeconnddaarryy Ho Hostst CPCPUU CPCPUU redundancredundancyy a and hnd hoost st with a hot-plug control/status register to support hot-plug 2 failover capabilitfailover capabilityy.. T Thhe e capability through external logic via the I C interface. NT port allows syNT port allows systestemms s to isolate hostto isolate host mem memooryry SerDes Power and Signal Management domdomains byains by prese presenting nting The PEX 8732 provides low power capability that is fully the processor sthe processor subsyubsysstemtem NTNT compliant with the PCIe power management specification as an endpoinas an endpoint ratht rather er PEX 8PEX 8773322 and supports software control of the SerDes outputs to NNoonn--TTrrananspspaarrenentt than anotherthan another PoPorrtt allow optimization of power and signal strength in a mememmooryry sy systestemm system. Furthermore, the SerDes block supports loop-back EEnd nd EEnd nd EEnd nd Base address Base address modes and advanced reporting of error conditions, PoPoiinntt PoPoiinntt PoPoiinntt registers arregisters are e used used which enables efficient management of the entire system. FiFigugurree 3 3.. NNoonn--TTrranansparsparenentt P Poorrtt to translate to translate addresses doorbell registers are used toaddresses doorbell registers are used to send interrupt send interrupts s Interoperability between the abetween the address domains and scratcddress domains and scratchpad registers hpad registers The PEX 8732 is designed to be fully compliant with the (acc(accessible bessible byy both CPUs) allow inter-processor both CPUs) allow inter-processor PCI Express Base Specification r2.0, and is backwards cocommmmunicatiunication (see Figure 3).on (see Figure 3). compatible to PCI Express Base Specification r1.1 and PLX Technolo PLX Technologgyy, , www.plxtech.www.plxtech.com com Page 2 of 5Page 2 of 5 10/7/2010, Ve10/7/2010, Version 1.0rsion 1.0