Product Specification PE4307 75 RF Digital Attenuator 5-bit, 15.5 dB, 1 2000 MHz Product Description Features The PE4307 is a high linearity, 5-bit RF Digital Step Attenuation: 0.5 dB steps to 15.5 dB Attenuator (DSA) covering a 15.5 dB attenuation range in Flexible parallel and serial programming 0.5 dB steps. The device is pin compatible with the PE430x interfaces series. This 75-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates Latched or direct mode on a single 3-volt supply and maintains high attenuation Unique power-up state selection accuracy over frequency and temperature. It also has a Positive CMOS control logic unique control interface that allows the user to select an High attenuation accuracy and linearity initial attenuation state at power-up. The PE4307 exhibits over temperature and frequency very low insertion loss and low power consumption. This Very low power consumption functionality is delivered in a 4x4 mm QFN footprint. Single-supply operation 75 impedance The PE4307 is manufactured on Peregrines UltraCMOS Pin compatible with PE430x series process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance Packaged in a 20-lead 4x4 mm QFN of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type Switched Attenuator Array 20-lead 4x4 mm QFN RF Input RF Output Parallel Control 5 Control Logic Interface 3 Serial Control 1 Power-Up Control 71-0007 Table 1. Electrical Specifications +25C, V = 3.0V DD Parameter Test Condition Frequency Minimum Typical Maximum Unit Operation Frequency 1 2000 MHz 1 Insertion Loss 1 MHz 1.2 GHz - 1.4 1.95 dB Any Bit or Bit (0.15 + 4% of atten setting) dB Attenuation Accuracy 1 MHz 1.2 GHz - - Combination Not to exceed +0.25 dB dB 3,4 1 dB Compression 1 MHz 1.2 GHz 30 34 - dBm Two-tone inputs up to 1,2,4 Input IP3 1 MHz 1.2 GHz - 52 - dBm +18 dBm Return Loss Zo = 75 ohms 1 MHz 1.2 GHz 10 13 - dB 50% control to 0.5 dB Switching Speed - - 1 s of final value Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency 3. Note Absolute Maximum in Table 3 4. Measured in a 50 system Document No. 70-0161-05 www.psemi.com 2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE4307 Product Specification Figure 15. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Condition Min Max Unit V Power supply voltage -0.3 4.0 V DD V + DD V Voltage on any input -0.3 V I 0.3 N/C 1 15 C8 T Storage temperature range -65 150 C ST 20-lead RF1 2 14 RF2 P Input power (50) +30 dBm IN QFN Data 3 13 P/S ESD voltage (Human Body 4x4mm V 500 V ESD Model) Exposed Solder Pad 4 Clock 12 Vss/GND 5 LE 11 GND Table 4. Operating Ranges Parameter Min Typ Max Unit V Power Supply DD 2.7 3.0 3.3 V Voltage I Power Supply DD 100 A Current Table 2. Pin Descriptions Digital Input High 0.7xV V DD Pin Pin No. Description Name Digital Input Low 0.3xV V DD 1 N/C No connect Digital Input Leakage 1 A 2 RF1 RF port (Note 1) Input Power +24 dBm 3 Data Serial interface data input (Note 4) Temperature range -40 85 C 4 Clock Serial interface clock input 5 LE Latch Enable input (Note 2) Exposed Solder Pad Connection 6 V Power supply pin DD 7 N/C No connect The exposed solder pad on the bottom of the 8 PUP2 Power-up selection bit package must be grounded for proper device operation. 9 V Power supply pin DD 10 GND Ground connection Electrostatic Discharge (ESD) Precautions 11 GND Ground connection When handling this UltraCMOS device, observe the Negative supply voltage or GND 12 V /GND ss connection (Note 3) same precautions that you would use with other 13 P/S Parallel/Serial mode select ESD-sensitive devices. Although this device 14 RF2 RF port (Note 1) contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid 15 C8 Attenuation control bit, 8 dB exceeding the rate specified in Table 3. 16 C4 Attenuation control bit, 4 dB 17 C2 Attenuation control bit, 2 dB Latch-Up Avoidance 18 GND Ground connection. 19 C1 Attenuation control bit, 1 dB Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. 20 C0.5 Attenuation control bit, 0.5 dB Paddle GND Ground for proper operation Switching Frequency Notes: 1. Both RF ports must be held at 0 V or DC blocked with an external DC series capacitor The PE4307 has a maximum 25 kHz switching rate. 2. Latch Enable (LE) has an internal 100 k resistor to V DD 3. Connect pin 12 to GND to enable internal negative voltage Resistor on Pin 3 generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator 4. Place a 10 k resistor in series, as close to pin as possible to avoid A 10 k resistor on the input to Pin 3 (see Figure 5) frequency resonance. See Resistor on 3 paragraph will eliminate package resonance between the RF input pin and the digital input. Specified attenuation error versus frequency performance is dependent upon this condition. 2003-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0161-05 UltraCMOS RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: