Product Specification PE4308 75 RF Digital Attenuator 5-bit, 31 dB, DC 4.0 GHz Product Description Features The PE4308 is a high linearity, 5-bit RF Digital Step Attenuator Attenuation: 1 dB steps to 31 dB (DSA) covering 31 dB attenuation range in 1dB steps, and is Flexible parallel and serial programming pin compatible with the PE430x series. This 75-ohm RF DSA interfaces provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and Latched or direct mode maintains high attenuation accuracy over frequency and Unique power-up state selection temperature. It also has a unique control interface that allows Positive CMOS control logic the user to select an initial attenuation state at power-up. The High attenuation accuracy and linearity PE4308 exhibits very low insertion loss and low power over temperature and frequency consumption. This functionality is delivered in a 4x4 mm QFN Very low power consumption footprint. Single-supply operation 75 impedance The PE4308 is manufactured on Peregrines UltraCMOS Pin compatible with PE430x series process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance Packaged in a 20 Lead 4x4 mm QFN of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 20 Lead 4x4 mm QFN Switched Attenuator Array RF Input RF Output 5 Parallel Control Control Logic Interface 3 Serial Control 2 Power-Up Control Table 1. Electrical Specifications +25C, V = 3.0 V DD Parameter Test Conditions Frequency Minimum Typical Maximum Units Operation Frequency DC 2000 MHz 2 Insertion Loss DC 1.2 GHz - 1.4 1.95 dB Any Bit or Bit (0.2 + 4% of atten setting) dB Attenuation Accuracy DC 1.2 GHz - - Combination Not to Exceed +0.4 dB dB 1 dB Compression3,4 1 MHz 1.2 GHz 30 34 - dBm Two-tone inputs up to 1,2,4 Input IP3 1 MHz 1.2 GHz - 52 - dBm +18 dBm Return Loss DC 1.2 GHz 10 13 - dB 50% control to 0.5 dB Switching Speed - - 1 s of final value Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. See figures on Pages 4 to 6 for data across frequency. 3. Note Absolute Maximum in Table 3. 4. Measured in a 50 system. Document No. 70-0162-04 www.psemi.com 2003-2006 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE4308 Product Specification Figure 14. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V Power supply voltage -0.3 4.0 V DD V + DD V Voltage on any input -0.3 V I 0.3 1 C16 15 C8 T Storage temperature range -65 150 C ST 20-lead 2 14 RF1 RF2 P Input power (50) +30 dBm IN QFN 3 13 Data P/S ESD voltage (Human Body 4x4mm V 500 V ESD Model) Exposed Solder Pad Clock 4 12 Vss/GND LE 5 11 GND Table 4. Operating Ranges Parameter Min Typ Max Units V Power Supply DD 2.7 3.0 3.3 V Voltage I Power Supply DD 100 A Current Table 2. Pin Descriptions Digital Input High 0.7xV V DD Pin Pin Description Digital Input Low 0.3xV V DD No. Name 1 C16 Attenuation control bit, 16dB (Note 4). Digital Input Leakage 1 A 2 RF1 RF port (Note 1). Input Power +24 dBm 3 Data Serial interface data input (Note 4). Temperature range -40 85 C 4 Clock Serial interface clock input. 5 LE Latch Enable input (Note 2). Exposed Solder Pad Connection 6 V Power supply pin. DD 7 PUP1 Power-up selection bit. The exposed solder pad on the bottom of the package must be grounded for proper device 8 PUP2 Power-up selection bit. operation. 9 V Power supply pin. DD 10 GND Ground connection. Electrostatic Discharge (ESD) Precautions 11 GND Ground connection. When handling this UltraCMOS device, observe Negative supply voltage or GND 12 V /GND ss connection (Note 3) the same precautions that you would use with other 13 P/S Parallel/Serial mode select. ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to 14 RF2 RF port (Note 1). ESD, precautions should be taken to avoid 15 C8 Attenuation control bit, 8 dB. exceeding the rate specified in Table 3. 16 C4 Attenuation control bit, 4 dB. 17 C2 Attenuation control bit, 2 dB. Latch-Up Avoidance 18 GND Ground connection. Unlike conventional CMOS devices, UltraCMOS 19 C1 Attenuation control bit, 1 dB. devices are immune to latch-up. 20 N/C No connect Paddle GND Ground for proper operation Switching Frequency Notes: 1: Both RF ports must be held at 0 V or DC blocked with an DC The PE4308 has a maximum 25 kHz switching rate. external series capacitor. 2: Latch Enable (LE) has an internal 100 k resistor to V DD. Resistor on Pin 1 & 3 3: Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to V (-V ) to bypass and SS DD A 10 k resistor on the inputs to Pin 1 & 3 (see disable internal negative voltage generator. Figure 5) will eliminate package resonance between 4. Place a 10 k resistor in series, as close to pin as possible to avoid frequency resonance. See Resistor on Pin 1 & 3 the RF input pin and the two digital inputs. Specified paragraph attenuation error versus frequency performance is dependent upon this condition. 2003-2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0162-04 UltraCMOS RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: