PE4314 Document Category: Product Specification UltraCMOS RF Digital Step Attenuator, 1 MHz2.5 GHz Features Figure 1 PE4314 Functional Diagram Attenuation step of 0.5 dB up to 31.5 dB Glitch-less attenuation state transitions Switched Attenuator Array RF RF Low distortion for CATV and multi-carrier applica- Input Output tions Extended +105 C operating temperature Parallel and Serial programming interfaces Packaging 20-lead 4 4 0.85 mm QFN Applications Parallel Control DOCSIS 3.1/0 customer premises equipment 6-bit (CPE) and infrastructure Satellite CPE and infrastructure Serial Control Logic Interface Control Fiber CPE and infrastructure 3-bit Power-up Control 2-bit P/S V SS EXT (optional) Product Description The PE4314 is a 75 HaRP technology-enhanced, 6-bit RF digital step attenuator (DSA) that supports a frequency range from 1 MHz to 2.5 GHz. It features glitch-less attenuation state transitions and supports 1.8V control voltage and an extended operating temperature range up to +105 C, making this device ideal for multiple wired broadband applications. The PE4314 is a pin-compatible upgraded version of the PE4304, PE4307, PE4308 and PE43404. An integrated digital control interface supports both Serial and Parallel programming of the attenuation, including the capability to program an initial attenuation state at power up. The PE4314 covers a 31.5 dB attenuation range in a 0.5 dB step. It is capable of maintaining 0.5 dB monoto- nicity through 2.5 GHz. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE4314 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. 20152016, Peregrine Semiconductor Corporation. All rights reserved. Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-81718-1 (02/2017) www.psemi.comPE4314 RF Digital Step Attenuator Peregrines HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Optional External V SS For proper operation, the V pin must be grounded or tied to the V voltage specified in Table 2. When the SS EXT SS V pin is grounded, FETs in the switch are biased with an internal negative voltage generator. For applica- SS EXT tions that require the lowest possible spur performance, V can be applied externally to bypass the internal SS EXT negative voltage generator. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE4314 Parameter/Condition Min Max Unit Supply voltage, V 0.3 5.5 V DD Digital input voltage 0.3 3.6 V RF input power, 75 130 MHz See Fig. 5 dBm 30 MHz2.5 GHz +30 dBm Storage temperature range 65 +150 C (1) 1500 V ESD voltage HBM , all pins (2) 1000 V ESD voltage CDM , all pins Notes: 1) Human body model (MIL-STD 883 Method 3015). 2) Charged device model (JEDEC JESD22-C101). Page 2 DOC-81718-1 (02/2017) www.psemi.com