PE29101 Document Category: Product Specification UltraCMOS High-speed FET Driver, 40 MHz Features Figure 1 PE29101 Functional Diagram High- and low-side FET drivers V DD Dead-time control Sync Boot Fast propagation delay, 11 ns VDDSYNC Switch Internal gate overvoltage management HSB UVLO HSG PU Output Level Sub-nanosecond rise and fall time Driver Shifter HSG PD 2A/4A peak source/sink current Dead HSS Time Logic IN Controller LSB Package flip chip EN LSG PU Level Output Shifter Driver RDHL LSG PD RDLH LSS Applications GND LSO DCDC conversions ACDC conversions Wireless power LiDAR Product Description The PE29101 integrated high-speed driver is designed to control the gates of external power devices, such as enhancement mode gallium nitride (GaN) FETs. The outputs of the PE29101 are capable of providing switching transition speeds in the sub-nanosecond range for switching applications up to 40 MHz. High switching speeds result in smaller peripheral components and enable new applications such as wireless power charging. The PE29101 operates from 4V to 6.5V and can support a high side floating supply voltage of 80V. An optional internal synchronous bootstrap circuit limits overcharging of the bootstrap capacitor during reverse body diode conduction, preventing the GaN FETs from exceeding their maximum gate-to-source voltage rating. The PE29101 also features a dead-time controller that allows timing of the LS and HS gates to eliminate any large shoot-through currents that could dramatically reduce the efficiency of the circuit and potentially damage the transistors. The PE29101 is available in a flip chip package and is manufactured on Peregrines UltraCMOS process, a patented advanced form of silicon-on-insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional CMOS. 2018, pSemi Corporation. All rights reserved. Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-78681-7 (07/2019) www.psemi.com END OF LIFEPE29101 High-speed FET Driver Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE29101 Parameter/Condition Min Max Unit Low-side bias (LSB) to low-side source (LSS) 0.3 7 V High-side bias (HSB) to high-side source (HSS) 0.3 7 V Input signal 0.3 7 V HSS to LSS 5 100 V (*) 1000 V ESD voltage HBM , all pins Note: * Human body model (JEDEC JS001, Table 2A). Page 2 of 15 DOC-78681-7 (07/2019) www.psemi.com END OF LIFE