Product Specification PE43404 75 RF Digital Attenuator 4-bit, 15 dB, DC 2.0 GHz Product Description Features The PE43404 is a high linearity, 4-bit RF Digital Step Attenuation: 1.0 dB steps to 15 dB Attenuator (DSA) covering a 15 dB attenuation range in 1.0 dB Flexible parallel and serial programming steps. This 75-ohm RF DSA provides both parallel (latched or interfaces direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy Parallel latched or direct mode over frequency and temperature. It also has a unique control High attenuation accuracy and linearity interface that allows the user to select an initial attenuation over temperature and frequency state at power-up. The PE43404 exhibits very low insertion Unique power-up state selection loss and low power consumption. This functionality is delivered Very low power consumption in a 4x4 mm QFN footprint. Single-supply operation Positive CMOS control logic The PE43404 is manufactured on Peregrines UltraCMOS 75 impedance process, a patented variation of silicon-on-insulator (SOI) Packaged in a 20 Lead 4x4 mm QFN technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type 20 Lead 4x4 mm QFN Switched Attenuator Array RF Input RF Output 5 Parallel Control 3 Control Logic Interface Serial Control 1 Power-Up Control Table 1. Electrical Specifications +25C, V = 3.0 V DD Parameter Test Conditions Frequency Minimum Typical Maximum Units Operation Frequency DC 2000 MHz 1 Insertion Loss DC 1.2 GHz - 1.4 1.95 dB Any Bit or Bit Attenuation Accuracy DC 1.2 GHz - - (0.25+ 7% of atten setting) dB Combination 3,4 1 dB Compression 1 MHz 1.2 GHz 30 34 - dBm Two-tone inputs up to 1,2,4 Input IP3 1 MHz 1.2 GHz - 52 - dBm +18 dBm Return Loss Zo = 75 ohms DC 1.2 GHz 10 13 - dB Switching Speed 50% control - - 1 s Notes: 1. Device Linearity will begin to degrade below 1MHz 2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency. 3. Note Absolute Maximum in Table 3. 4. Measured in a 50 system. Document No. 70-0258-01 www.psemi.com 2008 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43404 Product Specification Figure 15. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings Symbol Parameter/Conditions Min Max Units V Power supply voltage -0.3 4.0 V DD V + DD V Voltage on any input -0.3 V I 0.3 1 15 N/C C8 T Storage temperature range -65 150 C ST 20-lead 2 RF1 14 RF2 P Input power (50 ) +30 dBm QFN IN Data 3 13 P/S 4x4mm ESD voltage (Human Body V 500 V Exposed Solder Pad ESD 4 12 Clock Vss/GND Model) LE 5 11 GND Exceeding absolute maximum ratings may cause permanent damage. Operation should be restricted to the limits in the Operating Ranges table. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. Table 2. Pin Descriptions Pin Pin Table 4. Operating Ranges Description No. Name 1 N/C No connect Parameter Min Typ Max Units 2 RF1 RF port (Note 1). V Power Supply DD 2.7 3.0 3.3 V Voltage 3 Data Serial interface data input (Note 4). I Power Supply 4 Clock Serial interface clock input. DD 100 A Current 5 LE Latch Enable input (Note 2). Digital Input High 0.7xV V DD 6 V Power supply pin. DD 7 N/C No connect Digital Input Low 0.3xV V DD 8 PUP2 Power-up selection bit. Digital Input Leakage 1 A 9 V Power supply pin. DD 10 GND Ground connection. Input Power +24 dBm 11 GND Ground connection. Temperature range -40 85 C V / Negative supply voltage or GND ss 12 GND connection (Note 3) Electrostatic Discharge (ESD) Precautions 13 P/S Parallel/Serial mode select. When handling this UltraCMOS device, observe 14 RF2 RF port (Note 1). the same precautions that you would use with other 15 C8 Attenuation control bit, 8 dB. ESD-sensitive devices. Although this device 16 C4 Attenuation control bit, 4 dB. contains circuitry to protect it from damage due to 17 C2 Attenuation control bit, 2 dB. ESD, precautions should be taken to avoid 18 GND Ground connection. exceeding the rate specified in Table 3. 19 C1 Attenuation control bit, 1 dB. 20 GND Ground for proper operation Latch-Up Avoidance Paddle GND Ground for proper operation Unlike conventional CMOS devices, UltraCMOS Notes: 1. Both RF ports must be held at 0 V or DC blocked with DC devices are immune to latch-up. an external series capacitor. 2. Latch Enable (LE) has an internal 100 k resistor to V DD. Switching Frequency 3. Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to V (-VDD) to SS The PE43404 has a maximum 25 kHz switching rate. bypass and disable internal negative voltage generator. 4. Place a 10 k resistor in series, as close to pin as Resistor on Pin 3 possible to avoid frequency resonance. See Resistor on 3 paragraph A 10 k resistor on the input to Pin 3 (see Figure 5) Exposed Solder Pad Connection will eliminate package resonance between the RF input pin and the digital input. Specified attenuation The exposed solder pad on the bottom of the error versus frequency performance is dependent package must be grounded for proper device upon this condition. operation. 2008 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0258-01 UltraCMOS RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: