PE43508 Document Category: Product Specification UltraCMOS RF Digital Step Attenuator, 9 kHz55 GHz Features Figure 1 PE43508 Functional Diagram Wideband support up to 55 GHz Glitch-safe attenuation state transitions Switched Attenuator Array RF RF Flexible attenuation steps of 0.5 dB and 1 dB up to Input Output 31.5 dB Extended +105 C operating temperature Parallel and serial programming interfaces with serial addressability Flip-chip die Parallel Applications Control 6-bit Test and measurement (T&M) Point-to-point communication systems Serial In Serial Out Control Logic Interface Very small aperture terminals (VSAT) CLK LE (optional) A0 A1 A2 P/S V V DD SS EXT Product Description The PE43508 is a 50 , HaRP technology-enhanced, 6-bit RF digital step attenuator (DSA) that supports a wide frequency range from 9k to 55 GHz. The PE43508 features glitch-safe attenuation state transitions, supports 1.8V control voltage and optional V bypass mode to improve spurious performance, making this SS EXT device ideal for test and measurement, point-to-point communication systems, and very small aperture terminals (VSAT). The PE43508 provides an integrated digital control interface that supports both serial addressable and parallel programming of the attenuation. The PE43508 covers a 31.5 dB attenuation range in 0.5 dB and 1 dB steps. It is capable of maintaining 0.5 dB and 1 dB monotonicity through 55 GHz. In addition, no external blocking capac- itors are required if 0 VDC is present on the RF ports. The PE43508 is manufactured on pSemis UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology. 2018, pSemi Corporation. All rights reserved. Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-84244-4 (10/2018) www.psemi.comPE43508 RF Digital Step Attenuator pSemis HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. Optional External V Control SS For proper operation, the V control pin must be grounded or tied to the V voltage specified in Table 2. SS EXT SS When the V control pin is grounded, FETs in the switch are biased with an internal negative voltage SS EXT generator. For applications that require the lowest possible spur performance, V can be applied externally SS EXT to bypass the internal negative voltage generator. Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for the PE43508 Parameter/Condition Min Max Unit Positive supply voltage, V 0.3 5.5 V DD Negative supply voltage, V 3.6 0.3 V SS EXT Digital input voltage 0.3 3.6 V Peak RF input power, 50 Fig. 7 dBm Maximum junction temperature +150 C Storage temperature range 65 +150 C (*) 1000 V ESD voltage HBM, all pins Note: * Human body model (MILSTD 883 Method 3015) Page 2 of 25 DOC-84244-4 (10/2018) www.psemi.com