PE43601MLI-Z pSemi

Product Specification PE43601 50 RF Digital Attenuator 6-bit, 15.75 dB, 9 kHz - 6.0 GHz Product Description Features The PE43601 is a HaRP-enhanced, high linearity, 6-bit RF HaRP-enhanced UltraCMOS device Digital Step Attenuator (DSA). This highly versatile DSA covers a 15.75 dB attenuation range in 0.25 dB steps. The Attenuation: 0.25 dB steps to 15.75 dB Peregrine 50 RF DSA provides a serial-addressable CMOS High Linearity: Typical +58 dBm IIP3 control interface. It maintains high attenuation accuracy over Excellent low-frequency performance frequency and temperature and exhibits very low insertion loss and low power consumption. Performance does not change 3.3 V or 5.0 V Power Supply Voltage with V due to on-board regulator. This next generation DD Fast switch settling time Peregrine DSA is available in a 5x5 mm 32-lead QFN footprint. Programming Modes: Direct Parallel The PE43601 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) Latched Parallel technology on a sapphire substrate, offering the performance Serial-Addressable: Program up to of GaAs with the economy and integration of conventional eight addresses 000 - 111 CMOS. Serial Two-Byte Protocol: Address and Data Word High-attenuation state power-up (PUP) Figure 1. Package Type CMOS Compatible 32-lead 5x5x0.85 mm QFN Package No DC blocking capacitors required Packaged in a 32-lead 5x5x0.85 mm QFN Figure 2. Functional Schematic Diagram Switched Attenuator Array RF Output RF Input 6 Parallel Control Serial In Control Logic Interface CLK LE A0 A1 A2 P/S Document No. 70-0253-05 www.psemi.com 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43601 Product Specification Table 1. Electrical Specifications +25C, V = 3.3 V or 5.0 V DD Parameter Test Conditions Frequency Min Typical Max Units Frequency Range 9 kHz 6 GHz Attenuation Range 0.25 dB Step 0 15.75 dB Insertion Loss 9 kHz 6 GHz 2.3 2.8 dB 0 dB - 15.75 dB Attenuation settings 9 kHz < 4 GHz (0.2 + 4%) dB Attenuation Error 0 dB - 15.75 dB Attenuation settings 4 GHz 6 GHz (0.4 + 8%) dB Return Loss 9 kHz - 6 GHz 18 dB Relative Phase All States 9 kHz - 6 GHz 20 deg P1dB (note 1) Input 20 MHz - 6 GHz 30 32 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 6 GHz 57 dBm Typical Spurious Value 1 MHz -110 dBm Video Feed Through 10 mVpp Switching Time 50% CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns RF settled to within 0.05 dB of final value Settling Time 4 s RBW = 5 MHz, Averaging ON. Note 1. Please note Maximum Operating Pin (50 ) of +23dBm as shown in Table 3. Performance Plots Figure 3. 0.25 dB Step Error vs. Frequency* Figure 4. 0.25dB Attenuation vs. Attenuation State 200 MHz 900 MHz 1800 MHz 2200 MHz Attenuation 3000 MHz 4000 MHz 5000 MHz 6000 MHz 1.00 16 15 14 900 MHz 0.75 13 2200 MHz 12 3800 MHz 11 5800 MHz 10 0.50 9 8 7 0.25 6 5 4 0.00 3 2 1 0 -0.25 04 8 12 16 011 2 3 4 5 6 7 8 9 1011 121314156 Attenuation Setting (dB) Attenuation State *Monotonicity is held so long as step-error does not cross below -0.25 Figure 5. 0.25 dB Major State Bit Error Figure 6. 0.25 dB Attenuation Error vs. Frequency 0.25dB State 0.5dB State 1dB State 2dB State 200 MHz 900 MHz 1800 MHz 2200 MHZ 4dB State 8dB State 15.75dB State 3000 MHz 4000 MHz 5000 MHz 6000 MHz 1.5 1.5 1.0 1.0 0.5 0.5 0.0 0.0 -0.5 -0.5 -1.0 -1.0 -1.5 -1.5 0 1000 2000 3000 4000 5000 6000 04 8 12 16 Frequency (MHz) Attenuation Setting (dB) 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0253-05 UltraCMOS RFIC Solutions Page 2 of 13 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: