Product Specification PE43702 50 RF Digital Attenuator 7-bit, 31.75 dB, 9 kHz - 4.0 GHz Product Description Features The PE43702 is a HaRP-enhanced, high linearity, 7-bit RF Digital Step Attenuator (DSA). This highly versatile DSA HaRP-enhanced UltraCMOS device covers a 31.75 dB attenuation range in 0.25 dB steps. The Attenuation: 0.25 dB steps to 31.75 dB Peregrine 50 RF DSA provides both a serial and parallel CMOS control interface. It maintains high attenuation accuracy High Linearity: Typical +57 dBm IIP3 over frequency and temperature and exhibits very low insertion Excellent low-frequency performance loss and low power consumption. Performance does not 3.3 V or 5.0 V Power Supply Voltage change with V due to on-board regulator. This next DD generation Peregrine DSA is available in a 4x4 mm 24 lead Fast switch settling time QFN footprint. Programming Modes: Direct Parallel The PE43702 is manufactured on Peregrines UltraCMOS Latched Parallel process, a patented variation of silicon-on-insulator (SOI) Serial technology on a sapphire substrate, offering the performance High-attenuation state power-up (PUP) of GaAs with the economy and integration of conventional CMOS. CMOS Compatible No DC blocking capacitors required Figure 1. Package Type Packaged in a 24-lead 4x4x0.85 mm QFN 24-lead 4x4x0.85 mm QFN Package Figure 2. Functional Schematic Diagram RF Output RF Input 7 Parallel Control Serial In Control Logic Interface CLK LE P/S Document No. 70-0244-04 www.psemi.com 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: PE43702 Product Specification Table 1. Electrical Specifications +25C, V = 3.3 V or 5.0 V DD Parameter Test Conditions Frequency Min Typical Max Units Frequency Range 9 kHz 4.0 GHz Attenuation Range 0.25 dB Step 0 31.75 dB Insertion Loss 9 kHz - 4 GHz 2.0 2.5 dB (0.2 + 3%) 0 dB - 7.75 dB Attenuation settings 9 kHz - 4 GHz dB Attenuation Error 8 dB - 31.75 dB Attenuation settings 9 kHz - 4 GHz (0.3 + 4%) dB Return Loss 9 kHz - 4 GHz 18 dB Relative Phase All States 9 kHz - 4 GHz 44 deg P1dB (note 1) Input 20 MHz - 4 GHz 30 32 dBm IIP3 Two tones at +18 dBm, 20 MHz spacing 20 MHz - 4 GHz 57 dBm Typical Spurious Value 1MHz -110 dBm Video Feed Through 10 mVpp Switching Time 50% DC CTRL to 10% / 90% RF 650 ns RF Trise/Tfall 10% / 90% RF 400 ns RF settled to within 0.05 dB of final value. Settling Time 4 s RBW = 5 MHz, Averaging ON. Note 1. Please note Maximum Operating Pin (50 ) of +23dBm as shown in Table 3. Performance Plots Figure 3. 0.25dB Step Error vs. Frequency* Figure 4. 0.25dB Attenuation vs. Attenuation State 200 MHz 900 MHz 1800 MHz PE43702 Attenuation 2200 MHz 3000 MHz 4000 MHz 1 35 900 MHz 2200 MHz 30 3800 MHz 0.75 25 0.5 20 15 0.25 10 0 5 -0.25 0 0 4 8 12 16 20 24 28 32 035 10 152025 305 Attenuation Setting (dB) Attenuation State *Monotonicity is held so long as Step-Error does not cross below -0.25 Figure 5. 0.25dB Major State Bit Error Figure 6. 0.25dB Attenuation Error vs. Frequency 0.25dB 0.5dB 1dB 2dB 200MHz 900MHz 1800MHz 4dB 8dB 16dB 31.75dB 2200MHz 3000MHz 4000MHz 1.5 1.5 1 1 0.5 0.5 0 0 -0.5 -0.5 -1 -1 -1.5 -1.5 0 500 1000 1500 2000 2500 3000 3500 4000 0 4 8 1216 20242832 Frequency (MHz) Attenuation Setting (dB) 2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0244-04 UltraCMOS RFIC Solutions Page 2 of 11 Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: