PE45361 Document Category: Product Specification UltraCMOS Power Limiter, 10 MHz8 GHz Features Figure 1 PE45361 Functional Diagram Monolithic drop-in solution with no external bias components Adjustable low power limiting threshold from +7 dBm to +13 dBm P OUT High maximum power handling of 50 dBm, P1dB 100W pulsed RF1 RF2 Positive threshold control from +0V to +0.3V Fast response time of less than 1 ns Packaging 12-lead 3 3 0.5 mm QFN P IN Voltage Control and ESD Applications Wireless infrastructure transceivers and antennas Test and measurement (T&M) V CTRL Product Description The PE45361 is a HaRP technology-enhanced power limiter designed for use in high performance power limiting applications in test and measurement equipment and wireless infrastructure transceivers and antennas. Unlike traditional PIN diode solutions, the PE45361 achieves an adjustable input 1dB compression point or limiting threshold via a low current control voltage (V ), eliminating the need for external bias components CTRL such as DC blocking capacitors, RF choke inductors and bias resistors. It delivers low insertion loss and high linearity under non-limiting power levels and extremely fast response time in a limiting event, ensuring protection of sensitive circuitry. It also offers excellent ESD rating and ESD protection. The PE45361 is manufactured on pSemis UltraCMOS process, a patented advanced form of silicon-on- insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional CMOS. 2016-2020, pSemi Corporation. All rights reserved. Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-75388-6 (10/2020) www.psemi.comPE45361 UltraCMOS Power Limiter Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE45361 Parameter/Condition Min Max Unit Control voltage, V CTRL 03.6 V Power limiting mode (1) 50 dBm RF input power, Pulsed Storage temperature range 65 +150 C (2) 7000 V ESD voltage HBM, all pins (3) 2000 V ESD voltage CDM, all pins Notes: 1) Pulsed, 1.0% duty cycle of 10 s pulse width in 1 ms period, 50 at +25 C. 2) Human body model (MIL-STD 883 Method 3015). 3) Charged device model (JEDEC JESD22-C101). Page 2 of 15 DOC-75388-6 (10/2020) www.psemi.com