Part Number 856064 140 MHz SAW Filter Data Sheet Features For IF applications Typical 3dB bandwidth of 2 MHz High attenuation Single-ended operation Ceramic Surface Mount Package (SMP) Replaces Sawtek P/N 851905 (BW 3dB = 2.0MHz) Hermetic RoHS compliant (2002/95/EC), Pb-free Pb Package Pin Configuration Surface Mount 19.00 x 6.50 x 1.75 mm Bottom View SMP-75B 1 2 3 4 5 1.75 NOM. 1.96 MAX. 0.76 10 9 8 7 6 19.0 1.91 Single-ended Configuration 1.80 Pin No. Description R0.51 10 RF input 6.50 5 RF output 1,6 Ground 2.31 2,3,4 Case Ground 1.02 7,8,9 Case Ground Dimensions shown are nominal in millimeters All tolerances are 0.15mm except overall length and width +0.15mm/-0.10mm Body: Al O ceramic 2 3 Lid: Kovar, Ni plated Terminations: Au plating 0.5 - 1.0m, over a 2 6m Ni plating Subject to change or obsolescence without notice Rev C 03/08 TriQuint Semiconductor Page 1 of 5 Part Number 856064 140 MHz SAW Filter Data Sheet (1) Electrical Specifications (2) Operating Temperature Range: 0 to +70 C (3) (4) Parameter Minimum Typical Maximum Unit Center Frequency - 140 - MHz Minimum Insertion Loss - 21.50 22.186 dB (5) Lower 1 dB Band Edge - 139.06 139.155 MHz (5) Upper 1 dB Band Edge 140.845 140.94 - MHz (5) Lower 3 dB Band Edge - 138.91 138.978 MHz (5) Upper 3 dB Band Edge 141.022 141.09 - MHz (5) Lower 40 dB Band Edge 138.272 138.31 - MHz (5) Upper 40 dB Band Edge - 141.67 141.726 MHz Amplitude Variation 139.15 140.85 MHz - 0.5 1.0 dB p-p Phase Linearity 139.15 140.85 MHz - 1.8 3.5 p-p Group Delay Variation 139.15 140.85 MHz - 85 180 ns p-p (5) Relative Attenuation 15 136 MHz 60 64 - dB 144 220 MHz 45 56 - dB 220 230 MHz 38 46 - dB 230 250 MHz 45 65 - dB 250 260 MHz 26 31 - dB 260 350 MHz 45 65 - dB (6) Source Impedance (single-ended) - 50 - (6) Load Impedance (single-ended) - 50 - Substrate Material - Quartz - - Notes: 1. All specifications are based on the TriQuint test circuit shown below 2. In production, devices will be tested at room temperature to a guardbanded specification to ensure electrical compliance over temperature 3. Electrical margin has been built into the design to account for the variations due to temperature drift and manufacturing tolerances 4. Typical values are based on average measurements at room temperature 5. Relative to minimum insertion loss 6. This is the optimum impedance in order to achieve the performance shown Test Circuit: Actual matching values may vary due to PCB layout and parasitics 47nH 110nH 10 5 50 50 18pF 50 Single-ended Single-ended 50 1,2,3,4 Input Output 6,7,8,9 Subject to change or obsolescence without notice Rev C 03/08 TriQuint Semiconductor Page 2 of 5