IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY IDT2305B CLOCK BUFFER FEATURES: DESCRIPTION: Phase-Lock Loop Clock Distribution The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer, 10MHz to 133MHz operating frequency designed to address high-speed clock distribution applications. The zero Distributes one clock input to one bank of five outputs delay is achieved by aligning the phase between the incoming clock and Zero Input-Output Delay the output clock, operable within the range of 10 to 133MHz. Output Skew < 250ps The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts Low jitter <175 ps cycle-to-cycle one reference input, and drives out five low skew clocks. The -1H version 50ps typical cycle-to-cycle jitter (15pF, 66MHz) of this device operates, up to 133MHz frequency and has a higher drive IDT2305B-1 for Standard Drive than the -1 device. All parts have on-chip PLLs which lock to an input clock IDT2305B-1H for High Drive on the REF pin. The PLL feedback is on-chip and is obtained from the No external RC network required CLKOUT pad. In the absence of an input clock, the IDT2305B enters power Operates at 3.3V VDD down. In this mode, the device will draw less than 25 A, the outputs are Power down mode tri-stated, and the PLL is not running, resulting in a significant reduction of Available in SOIC and TSSOP packages power. The IDT2305B is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM 8 CLKOUT 3 CLK1 PLL 1 Control REF Logic 2 CLK2 5 CLK3 7 CLK4 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES APRIL 2016 1 c 2016 Integrated Device Technology, Inc.IDT2305B 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating Max. Unit VDD Supply Voltage Range 0.5 to +4.6 V (2) VI Input Voltage Range (REF) 0.5 to +5.5 V VI Input Voltage Range 0.5 to V 1 REF 8 CLKOUT (except REF) VDD+0.5 CLK2 2 CLK4 7 IIK (VI < 0) Input Clamp Current 50 mA IO (VO = 0 to VDD) Continuous Output Current 50 mA VDD 3 6 CLK1 VDD or GND Continuous Current 100 mA GND TA = 55C Maximum Power Dissipation 0.7 W 4 5 CLK3 (3) (in still air) TSTG Storage Temperature Range 65 to +150 C SOIC/TSSOP Operating Commercial Temperature 0 to +70 C TOP VIEW Temperature Range Operating Industrial Temperature -40 to +85 C Temperature Range NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. APPLICATIONS: SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number Type Functional Description REF 1 I N Input reference clock, 5 Volt tolerant input (1) CLK2 2 Out Output clock (1) CLK1 3 Out Output clock GND 4 Ground Ground (1) CLK3 5 Out Output clock VDD 6 PWR 3.3V Supply (1) CLK4 7 Out Output clock (1) CLKOUT 8 Out Output clock, internal feedback on this pin NOTES: 1. Weak pull down on all outputs. 2