23S09E-1HDCGI8 Renesas

IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 3.3V ZERO DELAY IDT23S09E CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE FEATURES: DESCRIPTION: Phase-Lock Loop Clock Distribution The IDT23S09E is a high-speed phase-lock loop (PLL) clock buffer, 10MHz to 200MHz operating frequency designed to address high-speed clock distribution applications. The zero Distributes one clock input to one bank of five and one bank of delay is achieved by aligning the phase between the incoming clock and four outputs the output clock, operable within the range of 10 to 200MHz. Separate output enable for each output bank The IDT23S09E is a 16-pin version of the IDT23S05E. The IDT23S09E Output Skew < 250ps accepts one reference input, and drives two banks of four low skew clocks. Low jitter <200 ps cycle-to-cycle The -1H version of this device operates up to 200MHz frequency and has IDT23S09E-1 for Standard Drive higher drive than the -1 device. All parts have on-chip PLLs which lock IDT23S09E-1H for High Drive to an input clock on the REF pin. The PLL feedback is on-chip and is No external RC network required obtained from the CLKOUT pad. In the absence of an input clock, the Operates at 3.3V VDD IDT23S09E enters power down. In this mode, the device will draw less Spread spectrum compatible than 12A for Commercial Temperature range and less than 25A for Available in SOIC and TSSOP packages Industrial temperature range, and the outputs are tri-stated. The IDT23S09E is characterized for both Industrial and Commercial operation. FUNCTIONAL BLOCK DIAGRAM 16 CLKOUT 2 CLKA1 PLL 1 REF 3 CLKA2 14 CLKA3 15 CLKA4 8 S2 Control 9 S1 Logic 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES MAY 2010 1 c 2006 Integrated Device Technology, Inc. DSC - 6399/11IDT23S09E 3.3V ZERO DELAY CLOCK BUFFER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Rating Max. Unit VDD Supply Voltage Range 0.5 to +4.6 V REF 1 16 CLKOUT (2) VI Input Voltage Range (REF) 0.5 to +5.5 V 2 CLKA1 15 CLKA4 VI Input Voltage Range 0.5 to V (except REF) VDD+0.5 CLKA2 3 14 CLKA3 IIK (VI < 0) Input Clamp Current 50 mA VDD 4 13 VDD IO (VO = 0 to VDD) Continuous Output Current 50 mA 5 GND GND 12 VDD or GND Continuous Current 100 mA TA = 55C Maximum Power Dissipation 0.7 W 6 CLKB1 11 CLKB4 (3) (in still air) CLKB2 7 CLKB3 10 TSTG Storage Temperature Range 65 to +150 C S2 8 Operating Commercial Temperature 0 to +70 C 9 S1 Temperature Range Operating Industrial Temperature -40 to +85 C SOIC/ TSSOP Temperature Range TOP VIEW NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation APPLICATIONS: of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating SDRAM conditions for extended periods may affect reliability. Telecom 2. The input and output negative-voltage ratings may be exceeded if the input and output Datacom clamp-current ratings are observed. PC Motherboards/Workstations 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils. Critical Path Delay Designs PIN DESCRIPTION Pin Name Pin Number Type Functional Description (1) REF 1 I N Input reference clock, 5 Volt tolerant input (2) CLKA1 2 Out Output clock for bank A (2) CLKA2 3 Out Output clock for bank A VDD 4, 13 PWR 3.3V Supply GND 5, 12 GND Ground (2) CLKB1 6 Out Output clock for bank B (2) CLKB2 7 Out Output clock for bank B (3) S2 8 I N Select input Bit 2 (3) S1 9 I N Select input Bit 1 (2) CLKB3 10 Out Output clock for bank B (2) CLKB4 11 Out Output clock for bank B (2) CLKA3 14 Out Output clock for bank A (2) CLKA4 15 Out Output clock for bank A (2) CLKOUT 16 Out Output clock, internal feedback on this pin NOTES: 1. Weak pull down. 2. Weak pull down on all outputs. 3. Weak pull ups on these inputs. 2