DATASHEET LOW SKEW 1 TO 4 CLOCK BUFFER ICS524 Description Features The ICS524 is a low skew, single input to four output, clock Extremely low skew outputs (50 ps maximum) TM buffer. Part of IDTs ClockBlocks family, this is our lowest Packaged in 8-pin SOIC skew, small clock buffer. Available in Pb (lead) free package See the ICS552-02 for a 1 to 8 low skew buffer. For more Low power CMOS technology TM than eight outputs, see the MK74CBxxx Buffalo series of Operating voltages of 2.5 V to 5 V clock drivers. 5 V tolerant input clock IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize Industrial temperature range clocks. Contact us for all of your clocking needs. Block Diagram Q0 Q1 ICLK Q2 Q3 IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER 1 ICS524 REV C 021909ICS524 LOW SKEW 1 TO 4 CLOCK BUFFER FAN OUT BUFFER Pin Assignment ICLK 1 8 GND Q0 2 7 Q3 Q1 3 6 Q2 NC 4 5 VDD 8-pin SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock input, 5V tolerant input. 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 NC Internal no connect. 5 VDD Power Connect to +2.5 V, +3.3 V or +5.0 V. 6 Q2 Output Clock Output 2. 7 Q3 Output Clock Output 3. 8 GND Power Connect to ground. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 5 and GND on pin 8, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the ICS524 is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15 ps of skew. IDT / ICS LOW SKEW 1 TO 4 CLOCK BUFFER 2 ICS524 REV C 021909