Low Skew 1 to 4 Clock Buffer 524S D ATA S HE E T Description Features The 524S is a low skew, single input to four output, clock Low additive phase jitter RMS: 50fs buffer. The 524S has best in class additive phase jitter of sub Extremely low skew outputs (50ps) 50 fsec. The 524S is Power Down Tolerant (PDT). PDT Low cost clock buffer designated inputs may be driven before VDD is applied, Packaged in 8-SOIC and 8-DFN, Pb-free without damage to the device. ICLK is PDT and may be driven before VDD is applied Renesas makes many non-PLL and PLL based low skew Direct-coupled signal path suitable for 1pps clocks output devices as well as Zero Delay Buffers to synchronize Input/Output clock frequency up to 200MHz clocks. Contact us for all of your clocking needs. Non-inverting output clock Ideal for networking clocks Operating Voltages: 1.8V to 3.3V Advanced, low power CMOS process Extended temperature range (-40C to +105C) Block Diagram Q0 Q1 ICLK Q2 Q3 AUGUST 9, 2021 1 2021 Renesas Electronics Corporation524S DATASHEET Pin Assignments ICLK 1 8 GND ICLK 1 8 GND Q0 2 7 Q3 Q0 2 7 Q3 Q1 3 6 Q2 Q1 3 6 Q2 NC 4 5 VDD NC 4 5 VDD 8-pin DFN 8-pin SOIC Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock input. This pin is Power Down Tolerant (PDT). 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 NC No connect. 5 VDD Power Connect to +1.8V, +2.5 V, or +3.3 V. 6 Q2 Output Clock Output 2. 7 Q3 Output Clock Output 3. 8 GND Power Connect to ground. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 5 and GND on pin 8, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 524S is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. LOW SKEW 1 TO 4 CLOCK BUFFER 2 AUGUST 9, 2021