DATASHEET CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ICS527-01 Description Features The ICS527-01 Clock Slicer is the most flexible way to Packaged as 28-pin SSOP (150 mil body) generate an output clock from an input clock with zero Synchronizes fractional clocks rising edges skew. The user can easily configure the device to Pin configurable multiplication/division ratio produce nearly any output clock that is multiplied or divided from the input clock. The part supports Slices frequency or period non-integer multiplications and divisions. A SYNC SYNC pulse output indicates aligned edges pulse indicates when the rising clock edges are aligned Input clock frequency of 600 kHz to 200 MHz with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 Output clock frequencies up to 160 MHz MHz and produces an output clock up to 160 MHz. Very low jitter The ICS527-01 aligns rising edges on ICLK and FBIN Duty cycle of 45/55 up to 160 MHz at a ratio determined by the reference and feedback Operating voltage of 3.3V dividers. Pin selectable drive strength For configurable clocks that do not require zero delay, Multiple outputs available when combined with use the ICS525. fanout buffers Industrial temperature version available Pb (lead) free package Block Diagram R6:R0 S1:S0 2xDRIVE GND VDD 2 2 72 PDTS Reference ICLK Divider CLK1 Feedback PLL FBIN Divider PDTS Divide 1 by 2 CLK2 SYNC 0 Feedback can come from PDTS DIV2 CLK1 or CLK2 OECLK2 (not both) 7 F6:F0 IDT / ICS CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 1 ICS527-01 REV G 051310ICS527-01 CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER Pin Assignment Frequency Range Table S1 S0 CLK1 Output Frequency (MHz) R5 1 28 R4 R6 2 27 Commercial (0 to 70C) Industrial (-40 to 85C) R3 DIV2 3 26 0 0 37 - 75 35 - 70 R2 S0 4 25 0 1 18 - 37 16 - 35 R1 S1 5 24 R0 1 0 4 - 10 4 - 8 VDD 6 23 VDD 1 1 75 -160 70 - 140 ICLK 7 22 CLK1 To cover the range from 10 to 18 MHz (0 to 70C) and 8 FBIN 8 21 CLK2 to 16 MHz (-40 to 85C), select address 01 to generate GND 9 20 GND 2x your desired output frequency, then configure CLK2 OECLK2 10 19 PDTS to generate CLK1/2. 2XDRIVE 11 18 F6 F0 12 17 F5 CLK2 Operation Table CLK Drive Select Table F1 13 16 F4 F2 14 15 F3 OECLK2 DIV2 CLK2 2XDRIVE Output Drive 0X Z 0 12 mA 28 pin 150 mil body SSOP 1 0 SYNC 1 25 mA 11 CLK1/2 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1,2, 24-28 R5, R6, Input Reference divider word input pins determined by user. Forms a binary number R0-R4 from 0 to 127. Internal pull-up resistor. 3 DIV2 Input Selects CLK2 function to output a SYNC signal or a divide by 2 of CLK1 based on the table above. Internal pull-up resistor. 4, 5 S0, S1 Input Select pins for output divider determined by user. See table above. Internal pull-up resistor. 6, 23 VDD Power Connect to VDD. 7 ICLK Input Reference clock input. 8 FBIN Input Feedback clock input. 9, 20 GND Power Connect to ground. 10 OECLK2 Input CLK2 Output Enable. CLK2 tri-stated when low. Internal pull-up resistor. 11 2XDRIVE Input Clock output drive strength doubled when high. Internal pull-up resistor. 12-18 F0-F6 Input Feedback divider word input pins determined by user. Forms a binary number from 0 to 127. Internal pull-up resistor. 19 PDTS Input Power Down. Active low. Turns off entire chip when low, both clock outputs are tri-stated. Internal pull-up resistor. 21 CLK2 Output Output clock 2. Can be SYNC output or a low skew divide by 2 of CLK1. 22 CLK1 Output Output clock 1. IDT / ICS CLOCK SLICER USER CONFIGURABLE ZERO DELAY BUFFER 2 ICS527-01 REV G 051310