Low Skew 2-input MUX and 1 to 8 Clock Buffer 552-02S DATASHEET Description Features The 552-02S is a low skew, single-input to eight- output clock Low RMS Additive Phase Jitter: 50fs buffer. The device offers a dual input with pin select for Low output skew: 50ps switching between two clock sources. It has best in class Operating Voltages of 1.8V to 3.3V Additive Phase Jitter of sub 50fsec Packaged in 16-pin TSSOP and 16-pin VFQFN, Pb-free IDT makes many non-PLL and PLL based low skew output Input clock multiplexer simplifies clock selection devices as well as Zero Delay Buffers to synchronize clocks. Output Enable pin tri-states outputs Contact us for all of your clocking needs. Input/Output clock frequency up to 200 MHz Low power CMOS technology 3.3V tolerant inputs Extended temperature (-40C to +105C) Block Diagram Q0 Q1 Q2 INA 1 Q3 Q4 INB 0 Q5 Q6 Q7 SELA OE 552-02S APRIL 18, 2017 1 2017 Integrated Device Technology, Inc.552-02S DATASHEET Pin Assignments OE 1 16 SELA VDD 2 15 VDD 16 15 14 13 OE 1 Q5 12 Q0 3 14 Q7 2 11 Q1 4 13 Q6 VDD Q4 Q2 5 12 Q5 Q0 3 10 GND Q3 6 11 Q4 4 9 INA Q1 5 67 8 GND 7 10 GND INB 8 9 INA 16 Pin TSSOP 16-pin VFQFN Input Source Select SELA Input 0INB 1INA Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor. 2 VDD Power Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 15. 3 Q0 Output Clock Output 0. 4 Q1 Output Clock Output 1. 5 Q2 Output Clock Output 2. 6 Q3 Output Clock Output 3. 7 GND Power Connect to ground. 8 INB Input Clock Input B. 3.3V tolerant. 9 INA Input Clock Input A. 3.3V tolerant. 10 GND Power Connect to ground. 11 Q4 Output Clock Output 4. 12 Q5 Output Clock Output 5. 13 Q6 Output Clock Output 6. 14 Q7 Output Clock Output 7. 15 VDD Power Connect to +1.8V, +2.5V or +3.3V. Must be the same as pin 2. 16 SELA Input Selects either INA or INB. Internal pull-up resistor. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and GND on pin 10, as close to the device as possible. A 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inch. To achieve the low output skews that the 552-02S is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. LOW SKEW 2-INPUT MUX AND 1 TO 8 CLOCK BUFFER 2 APRIL 18, 2017 Q2 SELA Q3 VDD Q7 GND INB Q6