DATASHEET LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER ICS552-02 Description Features The ICS552-02 is a low skew, single-input to eight- Extremely low skew outputs (50ps maximum) output clock buffer. The device offers a dual input with Packaged in 16 pin TSSOP pin select for switching between two clock sources. It is Pb (lead) free package TM part of IDTs ClockBlocks family. See the ICS553 for a 1 to 4 low skew buffer. For more than 8 outputs see Low power CMOS technology TM the MK74CBxxx Buffalo series of clock drivers. Operating Voltages of 2.5 V to 5 V Output Enable pin tri-states outputs IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to 5 V tolerant input clocks synchronize clocks. Contact us for all of your clocking Input/Output clock frequency up to 200 MHz needs. Input clock multiplexer simplifies clock selection Industrial temperature Block Diagram Q0 Q1 Q2 INA 1 Q3 Q4 INB 0 Q5 Q6 Q7 SELA OE IDT / ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER 1 ICS552-02 REV L 051310ICS552-02 LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER CLOCK MUX AND BUFFER Pin Assignment Input Source Select SELA Input OE 1 16 SELA 0 INB VDD 2 15 VDD Q0 3 14 Q7 1 INA Q1 4 13 Q6 Q2 5 12 Q5 Q3 6 11 Q4 GND 7 10 GND INB 8 9 INA 16 Pin TSSOP Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor. 2 VDD Power Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15. 3 Q0 Output Clock Output 0 4 Q1 Output Clock Output 1 5 Q2 Output Clock Output 2 6 Q3 Output Clock Output 3 7 GND Power Connect to ground. 8 INB Input Clock Input B. 5V tolerant input. 9 INA Input Clock Input A. 5V tolerant input. 10 GND Power Connect to ground. 11 Q4 Output Clock Output 4 12 Q5 Output Clock Output 5 13 Q6 Output Clock Output 6 14 Q7 Output Clock Output 7 15 VDD Power Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2. 16 SELA Input Selects either INA or INB. Internal pull-up resistor. External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 F should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and GND on pin 10, as close to the device as possible. A 33 series terminating resistor should be used on each clock output if the trace is longer than 1 inch. To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. IDT / ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER 2 ICS552-02 REV L 051310