570BILF Renesas

DATASHEET MULTIPLIER AND ZERO DELAY BUFFER ICS570 Description Features The ICS570 is a high-performance Zero Delay Buffer (ZDB) 8-pin SOIC package which integrates IDTs proprietary analog/digital Phase Available in Pb (lead) free package Locked Loop (PLL) techniques. The A version is Pin-for-pin replacement and upgrade to ICS570M recommended for 5 V designs and the B version for Functional equivalent to AV9170 (not a pin-for-pin TM 3.3 V designs. The chip is part of IDTs ClockBlocks replacement) family, and was designed as a performance upgrade to Low input to output skew of 300 ps max (>60 MHz meet todays higher speed and lower voltage requirements. outputs) The zero delay feature means that the rising edge of the Ability to choose between 14 different multipliers from input clock aligns with the rising edges of both output 0.5x to 32x clocks, giving the appearance of no delay through the Output clock frequency up to 170 MHz at 3.3 V device. There are two outputs on the chip, one being a Can recover degraded input clock duty cycle low-skew divide by two of the other output. The device Output clock duty cycle of 45/55 incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high Power Down and Tri-State Mode impedance state. Passes spread spectrum clock modulation Full CMOS clock swings with 25 mA drive capability at The ICS570 is ideal for synchronizing outputs in a large TTL levels variety of systems, from personal computers to data Advanced, low power CMOS process communications to graphics/video. By allowing off-chip feedback paths, the device can eliminate the delay through ICS570B has an operating voltage of 3.3 V (5%) other devices. ICS570A has an operating voltage of 5.0 V (5%) The ICS570 A and B versions were designed to improve Industrial temperature version available input to output jitter from the original ICS570M version, and are recommended for all new designs. Block Diagram ICLK Phase VCO CLK Detector, S1:0 Charge /2 Pump, and Loop CLK2 Filter divide FBIN by N External feedback can com e from CLK or CLK/2 (see table on page 2) IDT / ICS MULTIPLIER AND ZERO DELAY BUFFER 1 ICS570 REV K 073007ICS570 MULTIPLIER AND ZERO DELAY BUFFER ZDB AND MULTIPLIER Pin Assignment S1S1 88 11 CLCLK/K/22 VDDVDD 22 77 CLCLKK GNDGND 33 66 S0S0 ICICLKLK 44 55 FBINFBIN 8 pin (150 mil) SOIC Clock Multiplier Decoding Table (Multiplies Input clock by amount shown) FBIN from FBIN from ICS570B (3.3 V) ICS570A (5.0 V) S1 S0 CLK CLK/2 CLK CLK/2 CLK CLK/2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2* 1 6 pin 7 pin 8 pin 7 pin 8 0 0 Power Down and Tri-State - - 0 M x3 x1.5 x6 x3 3.75 to 28 2.5 to 25 0 1 x4 x2 x8 x4 2.75 to 19 2.5 to 19 M 0 x8 x4 x16 x8 2.5 to 9.5 2.5 to 9.5 M M x6 x3 x12 x6 2.5 to 12.5 2.5 to 12.5 M 1 x10 x5 x20 x10 2.5 to 7.5 2.5 to 7.5 1 0 x1 /2 x2 x1 11 to 85 5 to 75 1 M x16 x8 x32 x16 1.5 to 5 1.5 to 5 1 1 x2 x1 x4 x2 5.5 to 37.5 2.5 to 37.5 0 = connect directly to ground M = leave unconnected (self-biases to VDD/2) 1 = connect directly to VDD *Input range with CLK feedback is double that for CLK/2 IDT / ICS MULTIPLIER AND ZERO DELAY BUFFER 2 ICS570 REV K 073007