DATASHEET LOW PHASE NOISE ZERO DELAY BUFFER ICS571 Description Features The ICS571 is a high speed, high output drive, low phase Packaged in 8-pin SOIC (Pb free) noise Zero Delay Buffer (ZDB) which integrates IDTs Can function as low phase noise x2 multiplier proprietary analog/digital Phase Locked Loop (PLL) Low skew outputs. One is 2 of other techniques. IDT introduced the world standard for these devices in 1992 with the debut of the AV9170, and updated Input clock frequency up to 160 MHz at 3.3 V that with the ICS570. The ICS571, part of IDTs Phase noise of better than -100 dBc/Hz from 1 kHz to 1 ClockBlocks family, was designed to operate at higher MHz offset from carrier frequencies, with faster rise and fall times, and with lower Can recover poor input clock duty cycle phase noise. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both Output clock duty cycle of 45/55 at 3.3 V outputs, giving the appearance of no delay through the High drive strength for >100 MHz outputs device. There are two outputs on the chip, one being a Full CMOS clock swings with 25 mA drive capability at low-skew divide by two of the other. TTL levels The chip is ideal for synchronizing outputs in a large variety Advanced, low power CMOS process of systems, from personal computers to data Operating voltages of 3.0 to 5.5 V communications to video. By allowing offchip feedback paths, the ICS571 can eliminate the delay through other devices. The use of dividers in the feedback path will enable the part to multiply by more than two. Block Diagram IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER 1 ICS571 REV H 051310ICS571 LOW PHASE NOISE ZERO DELAY BUFFER ZDB AND MULTIPLIER/DIVIDER Pin Assignment Feedback Configuration Table and Frequency Ranges (at 3.3 V) Feedback From CLK CLK/2 Input Range CLK Input clock frequency Input clock frequency/2 20 to 160 MHz CLK/2 2x Input clock frequency Input clock frequency 10 to 80 MHz Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK CI Reference clock input. 2 VDD P Connect to +3.3 V or +5 V. Must be same as other VDD. 3 GND P Connect to ground. 4 CLK/2 O Clock output per table above. Low skew divide by two of pin 7 clock. 5 GND P Connect to ground. 6 VDD P Connect to +3.3 V or +5 V. Must be same as other VDD. 7 CLK O Clock output per table above. 8 FBIN CI Feedback clock input. Connect to CLK or CLK/2 per table above. Key: CI = clock input I = input O = output P = power supply connection. IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER 2 ICS571 REV H 051310