DATASHEET ZERO DELAY, LOW SKEW BUFFER ICS574 Description Features The ICS574 is a low jitter, low-skew, high performance Packaged in 8 pin narrow SOIC, Pb (lead) free PLL-based zero delay buffer for high speed applications. Zero input-to-output delay Based on IDTs proprietary low jitter Phase Locked Loop Four 1X outputs (PLL) techniques, the device provides four low skew outputs at speeds up to 160 MHz at 3.3 V. When one of the Output to output skew is less than 150 ps outputs is connected directly to FBIN, the rising edge of Output clocks up to 160 MHz at 3.3 V each output is aligned with the rising edge of the input External feedback path for output edge placement clock. External delay elements connected in the feedback loops will cause the outputs to occur before the inputs by Spread Smart technology works with spread spectrum the amount of propagation delay of the external element. clock generators Full CMOS outputs with 18 mA output drive capability at TTL levels at 3.3 V Advanced, low power, sub-micron CMOS process Operating voltage from 3.0 to 5.5 V Industrial temperature version available Block Diagram CLK1 CLK2 FBIN PLL CLKIN CLK3 CLK4 IDT/ ICS ZERO DELAY, LOW SKEW BUFFER 1 ICS574 REV G 051310ICS574 ZERO DELAY, LOW SKEW BUFFER ZDB Pin Assignment CLKIN 8 1 FBIN CLK1 2 7 CLK4 CLK2 3 6 CLK3 GND 5 4 VDD Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 CLKIN Input Clock input. Connect to input clock source. 2, 3, 6, 7 CLK1:4 Output Clock Outputs (4). 4 GND Power Connect to ground. 5 VDD Power Power supply. Connect both pins to same voltage (either 3.3 V or 5 V). 8 FBIN Input Feedback input. IDT/ ICS ZERO DELAY, LOW SKEW BUFFER 2 ICS574 REV G 051310