Programmable Fanout Buffer 5P 1103 D ATA S HE E T Description Features The 5P1103 is a programmable fanout buffer intended for Up to two high performance universal differential output high performance consumer, networking, industrial, pairs computing, and data-communications applications. Low RMS additive phase jitter: 0.2ps Configurations may be stored in on-chip One-Time Four banks of internal non-volatile in-system 2 Programmable (OTP) memory or changed using I C programmable or factory programmable OTP memory interface. 2 I C serial programming interface The outputs are generated from a single reference clock. The One additional LVCMOS output clock input reference can be crystal, external single-ended or Two universal output pairs: differential clock. The reference clock can come from one of Each configurable as one differential output pair or the two redundant clock inputs and is selected by CLKSEL two LVCMOS outputs pin. A glitchless manual switchover function allows one of the I/O Standards: redundant clocks to be selected during normal operation. See Single-ended I/Os: 1.8V to 3.3V LVCMOS reference clock input section for details. Differential I/Os - LVPECL, LVDS and HCSL Two select pins allow up to 4 different configurations to be Input frequency ranges: programmed and accessible using processor GPIOs or bootstrapping. The different selections may be used for LVCMOS Reference Clock Input (XIN/REF) 1MHz to different operating modes (full function, partial function, partial 200MHz power-down), regional standards (US, Japan, Europe) or LVDS, LVPECL, HCSL Differential Clock Input system production margin testing. (CLKIN, CLKINB) 1MHz to 350MHz 2 Crystal frequency range: 8MHz to 40MHz The device may be configured to use one of two I C addresses to allow multiple devices to be used in a system. Individually selectable output voltage (1.8V, 2.5V, 3.3V) for each output pair Redundant clock inputs with manual switchover Pin Assignment Programmable crystal load capacitance Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA Available in 24-pin VFQFPN 4mm x 4mm package -40 to +85C industrial temperature operation 24 23 22 21 20 19 1 18 V 2 DDO CLKIN 2 17 OUT2 CLKINB 3 16 OUT2B XOUT EPAD 4 XIN/REF V 15 DDA 5 14 V NC DDA 6 13 NC CLKSEL 7 8 9 10 11 12 24-pin VFQFPN R31DS0085EU0100 September 15, 2021 1 2021 Renesas Electronics Corporation SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V V 1 DDO DDA OUT1 NC OUT1B NC5P1103 DATASHEET Functional Block Diagram XIN/REF V 0 DDO XOUT OUT0 SEL I2CB V 1 DDO OUT1 CLKIN OUT1B CLKINB V 2 DDO OUT2 CLKSEL OUT2B SD/OE V DDA V DDA SEL1/SDA OTP SEL0/SCL and Control Logic V DDA V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE FANOUT BUFFER 2 R31DS0085EU0100 September 15, 2021