Programmable Fanout Buffer 5P1105 DATASHEET Description Features The 5P1105 is a programmable fanout buffer intended for Up to four high performance universal differential output high performance consumer, networking, industrial, pairs computing, and data-communications applications. Low RMS additive phase jitter: 0.2ps Configurations may be stored in on-chip One-Time Four banks of internal non-volatile in-system 2 Programmable (OTP) memory or changed using I C programmable or factory programmable OTP memory interface. 2 I C serial programming interface The outputs are generated from a single reference clock. The One additional LVCMOS output clock reference clock can come from one of the two redundant Four universal output pairs: clock inputs. A glitchless manual switchover function allows Each configurable as one differential output pair or two one of the redundant clocks to be selected during normal LVCMOS outputs operation. I/O Standards: Two select pins allow up to 4 different configurations to be programmed and accessible using processor GPIOs or Single-ended I/Os: 1.8V to 3.3V LVCMOS bootstrapping. The different selections may be used for Differential I/Os - LVPECL, LVDS and HCSL different operating modes (full function, partial function, partial Input frequency ranges: power-down), regional standards (US, Japan, Europe) or system production margin testing. LVCMOS Reference Clock Input (XIN/REF) 1MHz to 200MHz 2 The device may be configured to use one of two I C addresses to allow multiple devices to be used in a system. LVDS, LVPECL, HCSL Differential Clock Input (CLKIN, CLKINB) 1MHz to 350MHz Pin Assignment Crystal frequency range: 8MHz to 40MHz Individually selectable output voltage (1.8V, 2.5V, 3.3V) for each output pair Redundant clock inputs with manual switchover Programmable crystal load capacitance Individual output enable/disable Power-down mode 1.8V, 2.5V or 3.3V core V , V DDD DDA Available in 24-pin VFQFPN 4mm x 4mm package 24 23 22 21 20 19 1 18 V 2 DDO -40 to +85C industrial temperature operation CLKIN 2 17 OUT2 CLKINB XOUT 3 16 OUT2B EPAD 4 V 3 XIN/REF 15 DDO 5 14 V OUT3 DDA 6 13 OUT3B CLKSEL 8 9 10 11 12 7 24-pin VFQFPN 5P1105 FEBRUARY 21, 2019 1 2019 Integrated Device Technology, Inc. SD/OE OUT0 SEL I2CB V 0 SEL1/SDA DDO SEL0/SCL V DDD V 4 V 1 DDO DDO OUT1 OUT4 OUT1B OUT4B5P1105 DATASHEET Functional Block Diagram XIN/REF V 0 DDO XOUT OUT0 SEL I2CB V 1 DDO OUT1 CLKIN OUT1B CLKINB V 2 DDO OUT2 CLKSEL OUT2B SD/OE V 3 DDO OUT3 SEL1/SDA OUT3B OTP SEL0/SCL and Control Logic V 4 DDO OUT4 V DDA OUT4B V DDD Applications Ethernet switch/router PCI Express 1.0/2.0/3.0 Broadcast video/audio timing Multi-function printer Processor and FPGA clocking MSAN/DSLAM/PON Fiber Channel, SAN Telecom line cards 1 GbE and 10 GbE PROGRAMMABLE FANOUT BUFFER 2 FEBRUARY 21, 2019