2.5V Single Data Rate 1:10 Clock Buffer 5T907 Terabuffer PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATASHEET DESCRIPTION: FEATURES: The 5T907 2.5V single data rate (SDR) clock buffer is a user-selectable Guaranteed Low Skew < 125ps (max) single-ended or differential input to ten single-ended outputs buffer built on Very low duty cycle distortion advanced metal CMOS technology. The SDR clock buffer fanout from a High speed propagation delay < 2.5ns. (max) single or differential input to ten single-ended outputs reduces the loading Up to 250MHz operation on the preceding driver and provides an ef cient clock distribution network. Very low CMOS power levels The 5T907 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V 1.5V VDDQ for HSTL interface LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, Hot insertable and over-voltage tolerant inputs 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level 3-level inputs for selectable interface input signals that may be hard-wired to appropriate high-mid-low levels. Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input The 5T907 has two output banks that can be asynchronously enabled/ interface disabled. Multiple power and grounds reduce noise. Selectable differential or single-ended inputs and ten single-end- ed outputs 2.5V VDD Available in TSSOP package NOT RECOMMENDED FOR NEW DESIGNS For new designs use functional replacement 8T39S11 APPLICATIONS: Clock and signal distribution FUNCTIONAL BLOCK DIAGRAM 5T907 REVISION A APRIL 11, 2014 1 2015 Integrated Device Technology, Inc.5T907 DATA SHEET (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VDD Power Supply Voltage 0.5 to +3.6 V (2) VDDQ Output Power Supply 0.5 to +3.6 V VI Input Voltage 0.5 to +3.6 V (3) VO Output Voltage 0.5 to VDDQ +0.5 V (3) VREF Reference Voltage 0.5 to +3.6 V TSTG Storage Temperature 65 to +165 C TJ Junction Temperature 150 C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci cation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V. (1) CAPACITANCE (TA = +25C, F = 1.0MHz) Symbol Parameter Min Typ. Max. Unit CIN Input Capacitance 3.5 pF NOTE: 1. This parameter is measured at characterization but not tested. Capacitance applies to all inputs except RxS and TxS. TSSOP TOP VIEW RECOMMENDED OPERATING RANGE Symbol Description Min. Typ. Max. Unit TA Ambient Operating Temperature 40 +25 +85 C (1) VDD Internal Power Supply Voltage 2.4 2.5 2.6 V HSTL Output Power Supply Voltage 1.4 1.5 1.6 V (1) VDDQ Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 1.65 1.8 1.95 V 2.5V LVTTL Output Power Supply Voltage VDD V VT Termination Voltage VDDQ / 2 V NOTE: 1. All power supplies should operate in tandem if VDD or VDDQ is at a maximum, then VDDQ or VDD (respectively) should be at a maximum, and vice-versa. 2.5V SINGLE DATA RATE 2 REVISION A 4/14/15 1:10 CLOCK BUFFER TERABUFFER