GL 2.5V LVDS, 1:2 Clock Buffer TerabufferII IDT5T9302I PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPEMBER 7, 2016 DATA SHEET General Description Features The IDT5T9302I 2.5V differential clock buffer is a user-selectable Guaranteed low skew: 50ps (maximum) differential input to two LVDS outputs. The fanout from a differential Very low duty cycle distortion: 125ps (maximum) input to two LVDS outputs reduces loading on the preceding driver High speed propagation delay: 1.5ns (maximum) and provides an efficient clock distribution network. The IDT5T9302I Up to 450MHz operation can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A Selectable inputs single-ended 3.3V / 2.5V LVTTL input can also be used to translate Hot insertable and over-voltage tolerant inputs to LVDS outputs. The redundant input capability allows for an 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL asynchronous change-over from a primary clock source to a (3.3V), CML or LVDS input interface secondary clock source. Selectable reference inputs are controlled Selectable differential inputs to two LVDS outputs by SEL. Power-down mode The IDT5T9302I outputs can be asynchronously enabled/ disabled. 2.5V V When disabled, the outputs will drive to the value selected by the GL DD pin. Multiple power and grounds reduce noise. -40C to 85C ambient operating temperature Available in Lead-free (RoHS 6) package Not Recommended For New Designs Applications For functional replacement part use 8SLVP1102 Clock distribution Pin Assignment GND 1 20 A2 2 19 nA2 nPD nc 3 18 GND V 4 17 V DD DD nQ1 5 16 nQ2 Q1 6 15 Q2 V 7 14 V DD DD SEL 8 13 nG 9 12 nA1 GND 10 11 A1 Block Diagram IDT5T9302I 20-Lead TSSOP, E-Pad GL 4.4mm x 6.5mm x 0.925mm package body nG Q1 OUTPUT G Package CONTROL nQ1 Top View nPD A1 1 nA1 Q2 OUTPUT CONTROL nQ2 A2 0 nA2 SEL 5T9302 Rev A 12/16/14 1 2014 Integrated Device Technology, Inc.5T9302 DATA SHEET Table 1. Pin Descriptions Name Type Description (1, 4) A 1:2 Input Adjustable Clock input. A 1:2 is thetru side of the differential clock input. Complementary clock inputs. nA 1:2 is the complementary side of A 1:2 . For LVTTL single-ended operation, nA 1:2 should be set to the desired toggle voltage for A 1:2 : (1, 4) nA 1:2 Input Adjustable REF = 1650mV 3.3V LVTTL V 2.5V LVTTL VREF = 1250mV Gate control for differential outputs Q1, nQ1 and Q2, nQ2. When nG is LOW, the differential nG Input LVTTL outputs are active. When nG is HIGH, the differential outputs are asynchronously driven to (2) the level designated by GL . See Table 3A. Specifies output disable level. If HIGH,tru outputs disable HIGH andcomplementar GL Input LVTTL outputs disable LOW. If LOW,tru outputs disable LOW andcomplementar outputs disable HIGH. See Table 3A. Q 1:2 Output LVDS Clock outputs. nQ 1:2 Output LVDS Complementary clock outputs. Reference clock select. When LOW, selects A2 and nA2. When HIGH, selects A1 and nA1. SEL Input LVTTL See Table 3B. Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. nPD Input LVTTL Inputs and outputs are disabled. Bothtru and complementary outputs will pull to VDD. (3) Set HIGH for normal operation. V Power Power supply for the device core and inputs. DD GND Power Power supply return for all power. nc Unused No connect recommended to connect to GND. NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user s responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-up after asserting nPD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal. Table 2. Pin Characteristics (TA = +25C, F = 1.0MHz) Symbol Parameter Test Conditions Minimum Typical Maximum Units C Input Capacitance 3pF IN NOTE: This parameter is measured at characterization but not tested. Rev A 12/16/14 2 2.5V LVDS, 1:2 CLOCK BUFFER TERABUFFERII