Q4 A1 LVDS, 1:4 Clock Buffer Terabuffer 5T9304I DATA SHEET General Description Features The 5T9304I differential clock buffer is a user-selectable differential Guaranteed low skew: 50ps (maximum) input to four LVDS outputs. The fanout from a differential input to four Very low duty cycle distortion: 125ps (maximum) LVDS outputs reduces loading on the preceding driver and provides Propagation delay: 1.9ns (maximum) an efficient clock distribution network. The 5T9304I can act as a Up to 450MHz operation translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A Selectable inputs single-ended 3.3V / 2.5V LVTTL input can also be used to translate Hot insertable and over-voltage tolerant inputs to LVDS outputs. The redundant input capability allows for an 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), asynchronous change-over from a primary clock source to a LVPECL (3.3V), CML or LVDS input interface secondary clock source. Selectable reference inputs are controlled Selectable differential inputs to four LVDS outputs by SEL. 2.5V V DD The 5T9304I outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL -40C to 85C ambient operating temperature pin. Multiple power and grounds reduce noise. Available in lead-free (RoHS 6) package Applications Clock distribution Pin Assignment GND A2 1 24 2 23 A2 PD GND RESERVED 3 22 4 21 V V DD DD 5 20 Q3 Q1 6 19 Q3 Q1 Q2 Q4 7 18 Q2 8 17 V V DD 9 16 DD SEL GL 10 15 G 11 14 A1 GND 12 13 5T9304I 24-Lead TSSOP, E-Pad 4.40mm x 7.8mm x 0.925mm G Package Top View 5T9304I Rev A 5/13/15 1 2015 Integrated Device Technology, Inc.5T9304I DATA SHEET Block Diagram GL G Q1 OUTPUT CONTROL Q1 PD Q2 OUTPUT CONTROL Q2 A1 1 A1 Q3 OUTPUT CONTROL Q3 A2 Q4 OUTPUT 0 CONTROL A2 Q4 SEL LVDS, 1:4 CLOCK BUFFER TERABUFFER 2 Rev A 5/13/15