GL 2.5V LVDS, 1:2 Glitchless Clock Buffer 5T93GL02 TERABUFFER II PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 DATA SHEET General Description Features The 5T93GL02 2.5V differential clock buffer is a user-selectable Guaranteed low skew: <50ps (maximum) differential input to two LVDS outputs. The fanout from a differential Very low duty cycle distortion: <100ps (maximum) input to two LVDS outputs reduces loading on the preceding driver High speed propagation delay: <2.2ns (maximum) and provides an efficient clock distribution network. The 5T93GL02 Up to 450MHz operation can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A Selectable inputs single-ended 3.3V / 2.5V LVTTL input can also be used to translate Hot insertable and over-voltage tolerant inputs to LVDS outputs. The redundant input capability allows for a 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL glitchless change-over from a primary clock source to a secondary (3.3V), CML or LVDS input interface clock source up to 450MHz. Selectable inputs are controlled by SEL. Selectable differential inputs to two LVDS outputs During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain Power-down mode low for up to three clock cycles of the newly-selected clock, after At power-up, FSEL should be LOW which the outputs will start from the newly-selected input. A FSEL 2.5V V DD pin has been implemented to control the switchover in cases where -40C to 85C ambient operating temperature a clock source is absent or is driven to DC levels below the minimum specifications. Available in TSSOP package Recommends IDT5T9302 if glitchless input selection is not The 5T93GL02 outputs can be asynchronously enabled/disabled. required When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise. Not Recommended for New Designs For functional replacement use 8SLVP1102 Applications Clock distribution Pin Assignment GND 1 20 A2 2 19 A2 PD 3 18 GND FSEL V 4 17 V DD DD Q1 5 16 Q2 Q1 6 15 Q2 V 7 14 V DD DD 8 13 SEL G 9 12 A1 GND 10 11 A1 20-Lead TSSOP 4.4mm x 6.5mm x 0.925mm package body G Package Top View 5T93GL02 Rev A 3/11/15 1 2015 Integrated Device Technology, Inc.5T93GL02 DATA SHEET Block Diagram GL G Q1 OUTPUT CONTROL Q1 PD Q2 OUTPUT CONTROL Q2 A1 1 A1 A2 0 A2 SEL FSEL 2.5V LVDS, 1:2 GLITCHLESS CLOCK BUFFER TERABUFFER II 2 Rev A 3/11/15