621SDCGI Renesas

Low Skew 1 to 4 Clock Buffer 621S DATASHEET Description Features The 621S is a low cost, high-speed single input to four output Low additive phase jitter RMS: 50fs clock buffer. The 621S has best in class Additive Phase Jitter Extremely low skew outputs (50ps) of sub 50fsec. Low cost clock buffer IDT makes many non-PLL and PLL based low skew output Packaged in 8-pin SOIC and 8-pin DFN, Pb-free devices as well as Zero Delay Buffers to synchronize clocks. Input/Output clock frequency up to 200 MHz Contact IDT for all of your clocking needs. Non-inverting output clock Ideal for networking clocks Operating Voltages: 1.8V to 3.3V Output Enable mode tri-states outputs Advanced, low power CMOS process Extended temperature range (-40C to +105C) Block Diagram Q1 Q2 ICLK Q3 Q4 Output Enable 621S REVISION A 03/18/15 1 2015 Integrated Device Technology, Inc.621S DATASHEET Pin Assignment ICLK 1 8 OE ICLK 1 8 OE Q1 2 7 VDD Q1 2 7 VDD Q2 3 6 GND Q2 3 6 GND Q3 4 5 Q4 Q3 4 5 Q4 8 Pin (150 mil) SOIC 8-pin DFN Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK Input Clock input. Internal pull-up resistor. 2 Q1 Output Clock output 1. 3 Q2 Output Clock output 2. 4 Q3 Output Clock output 3. 5 Q4 Output Clock output 4. 6 GND Power Connect to ground. 7 VDD Power Connect +1.8V, +2.5V or +3.3V. 8 OE Input Output Enable. Tri-states outputs when low. Internal pull-up resistor. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01 F should be connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. LOW SKEW 1 TO 4 CLOCK BUFFER 2 REVISION A 03/18/15