DATASHEET LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ICS670-03 Description Features The ICS670-03 is a high speed, low phase noise, Zero Packaged in 16-pin SOIC Delay Buffer (ZDB) which integrates IDTs proprietary Pb (lead) free package, RoHS compliant analog/digital Phase Locked Loop (PLL) techniques. It is Clock inputs from 5 to 210 MHz (see page 2) identical to the ICS670-01, but with an increased maximum TM Patented PLL with low phase noise output frequency of 210 MHz. Part of IDTs ClockBlocks family, the parts zero delay feature means that the rising Output clocks up to 210 MHz at 3.3V edge of the input clock aligns with the rising edges of the 15 selectable on-chip multipliers outputs giving the appearance of no delay through the Power down mode available device. There are two identical outputs on the chip. The Low phase noise: -124 dBc/Hz at 10 kHz FBCLK should be used to connect to the FBIN. Each output Output enable function tri-states outputs has its own output enable pin. Low jitter 15 ps one sigma The ICS670-03 is ideal for synchronizing outputs in a large Advanced, low power, sub-micron CMOS process variety of systems, from personal computers to data Industrial temperature rated communications to video. By allowing off-chip feedback Operating voltage of 3.3 V or 5 V paths, the ICS670-03 can eliminate the delay through other devices. The 15 different on-chip multipliers work in a variety of applications. For other multipliers, including functional multipliers, see the ICS527. Block Diagram VDD OE1 3 Voltage ICLK Controlled FBCLK Phase Oscillator Detector, Charge Pump, and Divide by Loop Filter FBIN N CLK2 4 S3:S0 3 GND OE2 External Feedback from FBCLK is recommended. IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 1 ICS670-03 REV J 051310ICS670-03 LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER ZDB AND MULTIPLIER Pin Assignment Multiplier Select Table S3 S2 S1 S0 CLK2 (and FBCLK) Input Range (MHz) VDD 1 16 GND 0000 Low (Power down - entire chip) VDD 2 15 GND 0001 Input x1.333 18 - 157.5 VDD 3 14 GND 0010 Input x6 5 - 35 CLK2 4 13 S0 0011 Input x1.5 16.67 - 140 OE2 5 12 S1 0100 Input x3.333 7.5 - 63 FBCLK 6 11 S2 0101 Input x2.50 10 - 84 OE1 7 10 S3 0110 Input x4 6 - 52.5 FBIN 8 9 ICLK 0111 Input x1 25 - 210 1000 Input x2.333 11 - 90 1001 Input x2.666 10 - 78.75 1010 Input x12 5 - 17.5 1011 Input x3 8 - 70 1100 Input x10 5 - 21 1101 Input x5 6 - 42 1110 Input x8 5 - 26.25 1111 Input x2 12 - 105 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 - 3 VDD Input Power supply. Connect both pins to the same voltage (either 3.3 V or 5 V). 4 CLK2 Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 5 OE2 Input Output clock enable 2. Tri-states the clock 2 output when low. 6 FBCLK Output Clock output from VCO. Output frequency equals the input frequency times multiplier. 7 OE1 Input Output clock enable 1. Tri-states the feedback clock output when low. 8 FBIN Input Feedback clock input. 9 ICLK Input Clock input. Connect to a 5 - 210 MHz clock. 10 S3 Input Multiplier select pin 3. Determines outputs per table above. Internal pull-up. 11 S2 Input Multiplier select pin 2. Determines outputs per table above. Internal pull-up. 12 S1 Input Multiplier select pin 1. Determines outputs per table above. Internal pull-up. 13 S0 Input Multiplier select pin 0. Determines outputs per table above. Internal pull-up. 14 - 16 GND Power Connect to ground. IDT / ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER 2 ICS670-03 REV J 051310