DATASHEET QUADRACLOCK QUADRATURE DELAY BUFFER ICS672-01/02 Description Features The ICS672-01/02 are zero delay buffers that generate four Packaged in 16-pin SOIC output clocks whose phases are spaced at 90 intervals. Pb (lead) free package, RoHS compliant Based on IDTs proprietary low jitter Phase-Locked Loop Input clock range from 5 MHz to 150 MHz (depends on (PLL) techniques, each device provides five low-skew multiplier) outputs, with clock rates up to 84 MHz for the ICS672-01 and up to 135 MHz for the ICS672-02. By providing outputs Clock outputs from up to 84 MHz (ICS672-01) and up to delayed one quarter clock cycle, the device is useful for 135 MHz (ICS672-02) systems requiring early or late clocks. The ICS672-01/02 Zero input-output delay include multiplier selections of x0.5, x1, x2, x3, x4, x5, or x6. Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections They also offer a mode to power-down all internal circuitry and tri-state the outputs. In normal operation, output clock Four accurate (<250 ps) outputs with 0, 90, 180, and FBCLK is tied to the FBIN pin. 270 phase shift from ICLK, and one FBCLK (0) Separate supply for output clocks from 2.5 V to 5 V IDT manufactures the largest variety of clock generators Full CMOS outputs (TTL compatible) and buffers, and is the largest clock supplier in the world. Tri-state mode for board-level testing Includes Power-down for power savings Advanced, low power, sub-micron CMOS process 3.3 V to 5 V operating voltage Industrial temperature version available Block Diagram VDD GND VDDIO 2 3 IN CLK0 PLL CLK90 Multiplier and CLK180 Quadrature FBIN Generation CLK270 CLKFB 3 Control S2:S0 Logic Power Down plus Tri-state External Feedback IDT / ICS QUADRACLOCK QUADRATURE DELAY BUFFER 1 ICS672-01/02 REV L 051310ICS672-01/02 QUADRACLOCK QUADRATURE DELAY BUFFER ZERODELAYBUFFER Pin Assignment Output Clock Mode Select Table S2 S1 S0 Output Clocks ICLK 1 16 FBIN 0 0 0 Power-down + tri-state CLK90 2 15 FBCLK 00 1 x1 CLK180 3 14 CLK0 01 0 x2 CLK270 4 13 VDD 01 1 x3 VDDIO 5 12 GND 10 0 x4 GND 6 11 VDD 10 1 x5 GND 7 10 S2 11 0 x6 S0 8 9 S1 11 1 x0.5 Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 ICLK InputClock input. 2 CLK90 Output Clock output (90 delayed from CLK0). 3 CLK180 Output Clock output (180 delayed from CLK0). 4 CLK270 Output Clock output (270 delayed from CLK0). 5 VDDIO Power Supply voltage for input and output clocks. Must not exceed VDD. 6, 7, 12 GND Power Connect to ground. 8 S0 Input Select input 0. See table above. 9 S1 Input Select input 1. See table above. 10 S2 Input Select input 2. See table above. 11, 13 VDD Power Connect to 3.3 V or 5.0 V. 14 CLK0 Output Clock output phase aligned to ICLK. 15 FBCLK Output Feedback clock output (0 phase shift from CLK0). 16 FBIN Input Feedback clock input. in normal operation, connect to FBCLK. IDT / ICS QUADRACLOCK QUADRATURE DELAY BUFFER 2 ICS672-01/02 REV L 051310