HIGH-SPEED IDT7006S/L 16K x 8 DUAL-PORT STATIC RAM M/S = H for BUSY output flag on Master, Features M/S = L for BUSY input on Slave True Dual-Ported memory cells which allow simultaneous Busy and Interrupt Flags reads of the same memory location On-chip port arbitration logic High-speed access Full on-chip hardware support of semaphore signaling Military: 20/25/35/55/70ns (max.) between ports Industrial: 55ns (max.) Fully asynchronous operation from either port Commercial: 15/17/20/25/35/55ns (max.) Devices are capable of withstanding greater than 2001V Low-power operation electrostatic discharge IDT7006S Battery backup operation2V data retention Active: 750mW (typ.) TTL-compatible, single 5V (10%) power supply Standby: 5mW (typ.) Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin IDT7006L TQFP Active: 700mW (typ.) Industrial temperature range (40C to +85C) is available Standby: 1mW (typ.) for selected speeds IDT7006 easily expands data bus width to 16 bits or more Green parts available, see ordering information using the Master/Slave select when cascading more than one device Functional Block Diagram OER OEL CEL CER R/WL R/WR I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYL BUSYR A12R A12L Address MEMORY Address Decoder ARRAY Decoder A0L A0R 13 13 ARBITRATION CEL INTERRUPT CER OEL SEMAPHORE OER LOGIC R/WR R/WL SEML SEMR M/S (2) (2) INTL INTR 2738 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY outputs and INT outputs are non-tri-stated push-pull. OCTOBER 2008 1 2008 Integrated Device Technology, Inc. DSC- 2739/16IDT7006S/L High-Speed 16K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7006 is a high-speed 16K x 8 Dual-Port Static RAM. The a very low standby power mode. IDT7006 is designed to be used as a stand-alone 128K-bit Dual-Port RAM Fabricated using IDTs CMOS high-performance technology, these devices typically operate on only 750mW of power. Low-power (L) or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach versions offer battery backup data retention capability with typical power in 16-bit or wider memory system applications results in full-speed, error- consumption of 500W from a 2V battery. free operation without the need for additional discrete logic. The IDT7006 is packaged in a ceramic 68-pin PGA, an 68-pin quad flatpack, a PLCC, and a 64-pin thin quad flatpack, TQFP. Military grade This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for product is manufactured in compliance with the latest revision of MIL-PRF- reads or writes to any location in memory. An automatic power down 38535 QML, Class B, making it ideally suited to military temperature feature controlled by CE permits the on-chip circuitry of each port to enter applications demanding the highest level of performance and reliability. (1,2,3) Pin Configurations INDEX 11/06/01 987 6543 2 1 68676665 64 63 62 61 I/O2L 60 10 A5L I/O3L 59 11 A4L I/O4L 58 12 A3L I/O5L 57 13 A2L 56 GND 14 A1L 55 I/O6L 15 IDT7006J or F A0L (4) J68-1 54 I/O7L 16 INTL (4) F68-1 53 VCC BUSYL 17 52 GND 18 GND 68 Pin PLCC / Flatpack 51 I/O0R M/S 19 . (5) Top View 50 I/O1R 20 BUSYR 49 I/O2R 21 INTR 48 VCC 22 A0R I/O3R 47 23 A1R I/O4R 46 24 A2R I/O5R 45 25 A3R I/O6R 44 26 A4R 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 2739 drw 02 11/06/01 INDEX 1 A4L 48 I/O2L 2 A3L 47 I/O3L 3 A2L 46 I/O4L 4 A1L 45 I/O5L 5 44 A0L GND 6 43 INTL 7006PF I/O6L (4) 7 42 BUSYL PN-64 I/O7L 8 41 GND VCC 9 64 Pin TQFP 40 M/S GND (5) Top View 10 BUSYR 39 I/O0R . INTR 11 38 I/O1R 12 37 A0R I/O2R VCC 13 36 A1R NOTES: 14 I/O3R 35 A2R 1. All VCC pins must be connected to power supply. I/O4R 15 34 A3R 2. All GND pins must be connected to ground supply. I/O5R 16 A4R 33 3. J68-1 package body is approximately .95 in x .95 in. x .17 in. F68-1 package body is approximately .97 in x .97 in x .08 in. PN64-1 package body is approximately 14mm x 14mm x 1.4mm. 2739 drw 03 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking 2 I/O7R I/O1L N/C I/O0L OER N/C R/WR OEL SEMR R/WL CER SEML N/C CEL A13R N/C GND A13L A12R VCC A11R A12L A10R A11L A9R A10L A8R A9L A7R A8L A6R A7L A5R A6L I/O6R 17 I/O1L 64 I/O7R 18 I/O0L 63 19 OER OEL 62 R/WR 20 61 R/WL SEMR 21 60 SEML CER 22 CEL 59 A13R 23 A13L 58 24 GND 57 VCC 25 A12L A12R 56 A11L A11R 26 55 27 A10L A10R 54 28 A9L A9R 53 A8L A8R 29 52 A7R 30 A7L 51 31 A6L A6R 50 A5L A5R 32 49