7007S25PF Renesas

HIGH-SPEED 7007L 32K x 8 DUAL-PORT STATIC RAM Features True Dual-Ported memory cells which allow simultaneous M/S = H for BUSY output flag on Master, reads of the same memory location M/S = L for BUSY input on Slave High-speed access Interrupt Flag Commercial: 15ns (max.) On-chip port arbitration logic Industrial: 20ns (max.) Full on-chip hardware support of semaphore signaling Low-power operation between ports IDT7007L Fully asynchronous operation from either port Active: 850mW (typ.) TTL-compatible, single 5V (10%) power supply Standby: 1mW (typ.) Available in a 68-pin PLCC and a 80-pin TQFP IDT7007 easily expands data bus width to 16 bits or more Industrial temperature range (40C to +85C) is available using the Master/Slave select when cascading more than for selected speeds one device Green parts available, see ordering information Functional Block Diagram OEL OER CEL CER R/WR R/WL I/O0L-I/O7L I/O0R-I/O7R I/O I/O Control Control (1,2) (1,2) BUSYR BUSYL A14L A14R Address MEMORY Address Decoder ARRAY Decoder A0L A0R 15 15 ARBITRATION CEL INTERRUPT CER OEL SEMAPHORE OER LOGIC R/WR R/WL SEMR SEML M/S (2) (2) INTR INTL 2940 drw 01 NOTES: 1. (MASTER): BUSY is output (SLAVE): BUSY is input. 2. BUSY and INT outputs are non-tri-stated push-pull. SEPTEMBER 2019 1 DSC 2940/167007L High-Speed 32K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The reads or writes to any location in memory. An automatic power down IDT7007 is designed to be used as a stand-alone 256K-bit Dual-Port RAM feature controlled by CE permits the on-chip circuitry of each port to enter or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more a very LOW standby power mode. word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach Fabricated using CMOS high-performance technology, these de- in 16-bit or wider memory system applications results in full-speed, error- vices typically operate on only 850mW of power. free operation without the need for additional discrete logic. The IDT7007 is packaged in a 68-pin PLCC and an 80-pin thin This device provides two independent ports with separate control, quad flatpack TQFP. address, and I/O pins that permit independent, asynchronous access for (1,2,3) Pin Configurations 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 27 9 I/O7R I/O1L 28 8 N/C I/O0L OER 29 7 N/C 30 6 R/WR OEL 31 SEMR 5 R/WL CER 32 4 SEML A14R 33 3 CEL 7007 2 A13R 34 A14L (4) PLG68 35 1 GND A13L 68 A12R 36 VCC 68-Pin PLCC 37 67 A11R A12L Top View 38 66 A10R A11L 39 65 A10L A9R 40 64 A8R A9L 41 A7R 63 A8L 42 62 A6R A7L 43 61 A5R A6L 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2940 drw 02 NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately .95 in x .95 in x .17 in. 4. This package code is used to reference the package diagram. 2 A4R I/O6R A3R I/O5R A2R I/O4R A1R I/O3R A0R VCC INTR I/O2R BUSYR I/O1R M/S I/O0R GND GND BUSYL VCC INTL I/O7L A0L I/O6L A1L GND A2L I/O5L A3L I/O4L A4L I/O3L A5L I/O2L