HIGH-SPEED 3.3V 70V9089/79L 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM Features: True Dual-Ported memory cells which allow simultaneous Counter enable and reset features access of the same memory location Full synchronous operation on both ports High-speed clock to data access 4ns setup to clock and 1ns hold on all control, data, and Commercial: 7.5ns (max.) address inputs Industrial: 12ns (max.) Data input, address, and control registers Low-power operation Fast 7.5ns clock to data out in the Pipelined output mode IDT70V9089/79L Self-timed write allows fast cycle time Active: 429mW (typ.) 12ns cycle time, 83MHz operation in the Pipelined output mode Standby: 1.32mW (typ.) LVTTL- compatible, single 3.3V (0.3V) power supply Flow-Through or Pipelined output mode on either port via Available in a 100 pin Thin Quad Flatpack (TQFP) package the FT/PIPE pin Green parts available, see ordering information Dual chip enables allow for depth expansion without additional logic Functional Block Diagram R/WL R/WR OEL OER CE0L CE0R 1 1 CE1L CE1R 0 0 0/1 0/1 1 0 1 0 0/1 0/1 FT/PIPEL FT/PIPER , I/O0L - I/O7L I/O0R - I/O7R I/O I/O Control Control (1) (1) A15R A15L Counter/ Counter/ MEMORY A0R A0L Address Address CLKR CLKL ARRAY Reg. Reg. ADSR ADSL CNTENR CNTENL CNTRSTL CNTRSTR 3750 drw 01 NOTE: 1. A15X is a NC for IDT70V9079. SEPTEMBER 2019 1 DSC 3750/14 2019 Integrated Device Technology, Inc.70V9089/79L High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: With an input data register, the IDT70V9089/79 has been opti- The IDT70V9089/79 is a high-speed 64/32K x 8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to mized for applications having unidirectional or bidirectional data flow allow simultaneous access of any address from both ports. Registers on in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low control, data, and address inputs provide minimal setup and hold times. standby power mode. Fabricated using CMOS high-performance The timing latitude provided by this approach allows systems to be designed with very short cycle times. technology, these devices typically operate on only 429mW of power. (2,3,4) Pin Configurations 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC 50 NC 76 49 NC NC 77 NC A6R 78 48 A5R 79 47 I/O7R I/O6R A4R 80 46 45 A3R 81 I/O5R 44 A2R 82 I/O4R 43 A1R 83 I/O3R A0R 84 42 VDD 85 41 CNTENR I/O2R CLKR 86 40 I/O1R 70V9089/79 87 39 ADSR I/O0R (5) PNG100 VSS 88 38 VSS 89 37 VDD ADSL 100-PIN TQFP CLKL 90 TOP VIEW 36 I/O0L CNTENL 91 35 I/OIL A0L 34 VSS 92 A1L 93 33 I/O2L A2L 94 32 I/O3L 95 A3L 31 I/O4L A4L 96 30 I/O5L 97 A5L 29 I/O6L 98 A6L 28 I/O7L NC 99 27 NC 100 NC 26 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 3750 drw 02 NOTES: 1. A15X is a NC for IDT70V9079. 2. All Vcc pins must be connected to power supply. 3. All GND pins must be connected to ground. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6.422 NC NC NC NC A7R A7L A8L A8R A9R A9L A10L A10R A11R A11L A12R A12L A13R A13L A14R A14L (1) (1) A15L A15R NC NC VDD VSS NC NC NC NC NC NC NC NC CE0L CE0R CE1R CE1L CNTRSTL CNTRSTR R/WR R/WL OER OEL FT/PIPEL FT/PIPER VSS NC NC NC