70V9199L12PF Renesas

70V9199/099L HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: Counter enable and reset features True Dual-Ported memory cells which allow simultaneous Full synchronous operation on both ports access of the same memory location 4ns setup to clock and 1ns hold on all control, data, and High-speed clock to data access address inputs Commercial: 9ns (max.) Data input, address, and control registers Industrial: 9ns (max.) Fast 9 ns clock to data out in the Pipelined output mode Low-power operation Self-timed write allows fast cycle time IDT70V9199/099L 15ns cycle time, 66 MHz operation in Pipelined output mode Active: 500mW (typ.) LVTTL- compatible, single 3.3V (0.3V) power supply Standby: 1.5mW (typ.) Industrial temperature range (40C to +85C) is Flow-Through or Pipelined output mode on either port via available for selected speeds the FT/PIPE pins Available in a 100-pin Thin Quad Flatpack (TQFP) Dual chip enables allow for depth expansion without Green parts available, see ordering information additional logic Functional Block Diagram R/WR R/WL OEL OER CE0R CE0L 1 1 CE1R CE1L 0 0 0/1 0/1 1 0 1 0 0/1 0/1 FT/PIPEL FT/PIPER . (1) (1) I/O0R-I/O8R I/O0L-I/O8L I/O I/O Control Control A16L A16R Counter/ Counter/ MEMORY A0L A0R Address Address CLKL ARRAY CLKR Reg. Reg. ADSL ADSR CNTENR CNTENL CNTRSTR CNTRSTL 4859 drw 01 NOTE: 1. I/O0X - I/O7X for IDT70V9099. JULY 2019 1 2019 Integrated Device Technology, Inc. DSC-4859/970V9199/099L High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges Description: With an input data register, the IDT70V9199/099 has been optimized The IDT70V9199/099 is a high-speed128K x9/x8 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to for applications having unidirectional or bidirectional data flow in bursts. An allow simultaneous access of any address from both ports. Registers on automatic power down feature, controlled by CE0 and CE1, permits the control, data, and address inputs provide minimal setup and hold times. on-chip circuitry of each port to enter a very low standby power mode. Fabricated using CMOS high-performance technology, these devices The timing latitude provided by this approach allows systems to be designed with very short cycle times. typically operate on only 500mW of power. (1,2,3) Pin Configuration 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 7574 76 50 NC NC 49 A6R 77 NC 78 48 A5R I/O8R 47 A4R 79 I/O7R 46 A3R 80 I/O6R 81 45 A2R I/O5R 82 44 I/O4R A1R A0R 83 43 I/O3R 84 42 CNTENR VDD 41 CLKR 85 I/O2R 70V9199 86 40 ADSR I/O1R (4) PNG100 VSS 87 39 I/O0R 88 38 VSS VSS ADSL 89 37 VDD 100-Pin TQFP CLKL 90 36 I/O0L Top View CNTENL 91 35 I/O1L 92 34 A0L VSS 93 A1L 33 I/O2L 32 A2L 94 I/O3L . A3L 95 31 I/O4L A4L 96 30 I/O5L 97 A5L 29 I/O6L 98 A6L 28 I/O7L 99 NC 27 I/O8L NC 100 26 VSS 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 4859 drw 02 NOTES: 1. All VDD pins must be connected to power supply. 2. All VSS pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 6.422 NC NC NC NC A7L A7R A8L A8R A9L A9R A10L A10R A11R A11L A12R A12L A13R A13L A14R A14L A15L A15R A16L A16R VSS VDD NC NC NC NC NC NC NC NC CE0R CE0L CE1R CE1L CNTRSTR CNTRSTL R/WR R/WL OER OEL FT/PIPER FT/PIPEL GND NC NC NC